55 lines
1.1 KiB
Systemverilog
55 lines
1.1 KiB
Systemverilog
`timescale 1ns/100ps
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`default_nettype none
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/* verilator lint_off TIMESCALEMOD */
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module cmod_a7
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(input wire GCLK_i,
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input wire [1:0] BTN_i,
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inout wire [3:0] PMOD0,
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inout wire [3:0] PMOD1);
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/* Clock and reset */
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logic clock;
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logic reset;
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logic pll_lock;
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main_pll main_pll_inst
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(.clk_12(GCLK_i),
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.reset(BTN_i[1]),
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.locked(pll_lock),
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.clk_50(clock));
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pll_lock_reset #(.RESET_LEN(16)) reset_gen_impl
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(.pll_clock(clock),
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.pll_lock(pll_lock & (~BTN_i[1])),
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.reset(reset));
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/* ADCs connection */
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logic [11:0] ldata, rdata;
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logic lstrb, rstrb;
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dual_mcp3201_pmod #(.CLOCK_FREQ(50000000),
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.SAMPLE_RATE(44100)) brd
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(.clock, .reset,
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.ladc_ssn(PMOD0[0]),
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.ladc_clk(PMOD0[3]),
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.ladc_dat(PMOD0[2]),
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.radc_ssn(PMOD1[0]),
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.radc_clk(PMOD1[3]),
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.radc_dat(PMOD1[2]),
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.rdata, .rstrb,
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.ldata, .lstrb);
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/* Logic analyzer */
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ila ila_impl
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(.clk(clock),
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.probe0({ lstrb, ldata }),
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.probe1({ rstrb, rdata }));
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endmodule // cmod_a7
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