71 lines
1.4 KiB
Systemverilog
71 lines
1.4 KiB
Systemverilog
`timescale 1ps/1ps
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module tb_mcp3201;
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logic clock = 1'b0;
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logic reset = 1'b1;
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/* Master clock 10MHz (100ns period) */
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always #(100ns/2) clock <= ~clock;
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logic spi_clk;
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logic spi_ssn;
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logic spi_miso;
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logic [11:0] data;
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logic strb;
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spi_sclk_gen #(.CLOCK_FREQ(10000000), .SCLK_FREQ(50000 * 17)) spi_clk_g
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(.clock, .reset,
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.sclk_o(spi_clk));
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mcp3201 DUT
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(.clock, .reset,
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.spi_clk_i(spi_clk),
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.spi_ssn_o(spi_ssn),
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.spi_miso_i(spi_miso),
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.data_o(data),
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.strb_o(strb));
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always_ff @ (posedge clock)
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if (strb)
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$display("%15b", data);
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logic [14:0] ds;
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initial begin
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reset = 1'b1;
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repeat(10) @(posedge clock);
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reset = 1'b0;
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/* Send word 0 */
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wait(spi_ssn == 1'b0);
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ds = 15'bzz0_1010_1010_1010;
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for (int i = 0; i < 15; i ++) begin
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@(negedge spi_clk) spi_miso = ds[14];
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ds = ds << 1;
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end
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/* Send word 1 */
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wait(spi_ssn == 1'b1);
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wait(spi_ssn == 1'b0);
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ds = 15'bzz0_0101_0101_0101;
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for (int i = 0; i < 15; i ++) begin
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@(negedge spi_clk) spi_miso = ds[14];
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ds = ds << 1;
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end
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wait(spi_ssn == 1'b1);
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repeat(10) @(posedge clock);
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$finish;
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end
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initial begin
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$dumpfile("tb_mcp3201.vcd");
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$dumpvars;
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end
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endmodule // tb_mcp3201
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