52 lines
1.2 KiB
Systemverilog
52 lines
1.2 KiB
Systemverilog
`timescale 1ns/100ps
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`default_nettype none
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module dual_mcp3201_pmod #(parameter CLOCK_FREQ = 25000000,
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parameter SAMPLE_RATE = 50000)
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(input wire clock,
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input wire reset,
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output wire radc_ssn,
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output wire radc_clk,
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input wire radc_dat,
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output wire ladc_ssn,
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output wire ladc_clk,
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input wire ladc_dat,
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output wire [11:0] rdata,
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output wire rstrb,
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output wire [11:0] ldata,
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output wire lstrb);
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localparam MCP3201_CLOCK_PER_SAMPLE = 17;
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localparam SCLK_FREQ = SAMPLE_RATE * MCP3201_CLOCK_PER_SAMPLE;
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logic spi_clk;
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spi_sclk_gen #(.CLOCK_FREQ(CLOCK_FREQ),
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.SCLK_FREQ(SCLK_FREQ)) spi_sclk_gen_impl
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(.clock, .reset,
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.sclk_o(spi_clk));
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mcp3201 adc_left
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(.clock, .reset,
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.spi_clk_i(spi_clk),
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.spi_ssn_o(ladc_ssn),
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.spi_miso_i(ladc_dat),
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.data_o(ldata),
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.strb_o(lstrb));
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mcp3201 adc_right
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(.clock, .reset,
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.spi_clk_i(spi_clk),
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.spi_ssn_o(radc_ssn),
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.spi_miso_i(radc_dat),
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.data_o(rdata),
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.strb_o(rstrb));
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assign ladc_clk = spi_clk;
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assign radc_clk = spi_clk;
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endmodule // dual_mcp3201_pmod
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