18 lines
410 B
Systemverilog
18 lines
410 B
Systemverilog
`timescale 1ns/100ps
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`default_nettype none
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module pll_lock_reset #(parameter RESET_LEN = 8)
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(input wire pll_clock,
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input wire pll_lock,
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output wire reset);
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logic [RESET_LEN:0] rst_sr;
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always_ff @(posedge pll_clock, negedge pll_lock)
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if (~pll_lock) rst_sr <= '0;
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else rst_sr <= { 1'b1, rst_sr[RESET_LEN:1] };
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assign reset = ~rst_sr[0];
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endmodule // pll_lock_reset
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