35 lines
893 B
Systemverilog
35 lines
893 B
Systemverilog
`timescale 1ns/100ps
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`default_nettype none
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module spi_sclk_gen #(parameter CLOCK_FREQ = 12000000,
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parameter SCLK_FREQ = 50000)
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(input wire clock,
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input wire reset,
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output reg sclk_o);
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localparam SCLK_PERIOD = integer'($floor(real'(CLOCK_FREQ)/real'(SCLK_FREQ) + 0.5));
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localparam SCLK_HPER = SCLK_PERIOD/2;
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localparam SCLK_CW = $clog2(SCLK_PERIOD);
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logic [SCLK_CW-1:0] sclk_cnt;
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always_ff @(posedge clock)
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if (reset) begin
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sclk_cnt <= '0;
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sclk_o <= 1'b0;
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end
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else begin
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if (sclk_cnt == '0)
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sclk_o <= 1'b0;
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else
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if (sclk_cnt == SCLK_CW'(SCLK_HPER))
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sclk_o <= 1'b1;
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if (sclk_cnt == SCLK_CW'(SCLK_PERIOD-1))
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sclk_cnt <= '0;
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else
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sclk_cnt <= sclk_cnt + 1'b1;
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end
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endmodule // spi_sclk_gen
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