From 6ae8b4fc26ed9de321fc4e353905af5357dd4956 Mon Sep 17 00:00:00 2001
From: Nikolay Puzanov <np@embddr.xyz>
Date: Sat, 10 Jan 2026 17:22:59 +0300
Subject: [PATCH] Add continuous mode to HNY2026

Implemented a new `continuous` flag in `HnyConfig` and added a `sent` register in `HNY2026` to track
whether the message has been fully transmitted. When `continuous` is `false`, the module stops
sending after one full cycle.
---
 hny2026/src/Hny2026.scala      | 10 ++++++++--
 hny2026/src/HnyConfig.scala    |  5 ++++-
 hny2026/src/TestGen.scala      | 15 ++++++++++++++-
 hny2026/test/src/Hny2026.scala | 12 ++++++++++--
 4 files changed, 36 insertions(+), 6 deletions(-)

diff --git a/hny2026/src/Hny2026.scala b/hny2026/src/Hny2026.scala
index 83103e9..6749ff0 100644
--- a/hny2026/src/Hny2026.scala
+++ b/hny2026/src/Hny2026.scala
@@ -143,13 +143,18 @@ class HNY2026(cfg: HnyConfig, str: String) extends Module {
   val sender = Module(new CharSender(cfg))
   val chars = VecInit(str.map(_.toByte.U(cfg.dataWidth.W)))
   val charCnt = RegInit(UInt(log2Up(str.length()).W), 0.U)
+  val sent = RegInit(false.B)
 
-  sender.io.data.valid := true.B
+  sender.io.data.valid := !sent
   sender.io.data.bits := chars(charCnt)
 
   when(sender.io.data.ready) {
     when(charCnt === (chars.length - 1).U) {
       charCnt := 0.U
+
+      if(!cfg.continuous) {
+        sent := true.B
+      }
     } otherwise {
       charCnt := charCnt + 1.U
     }
@@ -188,7 +193,8 @@ object HNY2026 extends App {
     clockFreq = clockFreq,
     frameRate = 30,
     frameRateAccuracy = 0.0001,
-    dataWidth = 8
+    dataWidth = 8,
+    continuous = true
   )
 
   ChiselStage.emitSystemVerilogFile(
diff --git a/hny2026/src/HnyConfig.scala b/hny2026/src/HnyConfig.scala
index 080b8d2..6dabe85 100644
--- a/hny2026/src/HnyConfig.scala
+++ b/hny2026/src/HnyConfig.scala
@@ -26,10 +26,13 @@ import chisel3.util._
  *                           stream is `dataWidth + 2` bits, the
  *                           additional bits being a parity bit and a
  *                           empty ending bit.
+ * @param continuous         If true, the display will cycle continuously.
+ *                           If false, the display will show the message once and stop.
  */
 case class HnyConfig(
   clockFreq: Int = 27000000,
   frameRate: Double = 30.0,
   frameRateAccuracy: Double = 0.0001,
-  dataWidth: Int = 8
+  dataWidth: Int = 8,
+  continuous: Boolean = true
 )
diff --git a/hny2026/src/TestGen.scala b/hny2026/src/TestGen.scala
index c305b56..cad162f 100644
--- a/hny2026/src/TestGen.scala
+++ b/hny2026/src/TestGen.scala
@@ -35,7 +35,20 @@ object TestGen_CharSender extends App {
  */
 object TestGen_HNY2026 extends App {
   println(ChiselStage.emitSystemVerilog(
-    new HNY2026(HnyConfig(27000000, 30.3), "Hello!"),
+    new HNY2026(HnyConfig(27000000, 30.3, continuous = false), "Hello!"),
+    firtoolOpts = Array(
+      "--disable-all-randomization",
+      "--strip-debug-info"
+    )
+  ))
+}
+
+/**
+ * Run: mill hny2026.runMain hny2026.TestGen_HNY2026_Continuous
+ */
+object TestGen_HNY2026_Continuous extends App {
+  println(ChiselStage.emitSystemVerilog(
+    new HNY2026(HnyConfig(27000000, 30.3, continuous = true), "Hello!"),
     firtoolOpts = Array(
       "--disable-all-randomization",
       "--strip-debug-info"
diff --git a/hny2026/test/src/Hny2026.scala b/hny2026/test/src/Hny2026.scala
index e77ba66..576158c 100644
--- a/hny2026/test/src/Hny2026.scala
+++ b/hny2026/test/src/Hny2026.scala
@@ -175,8 +175,16 @@ class HNY2026Test extends AnyFlatSpec with ChiselSim {
 
   behavior of "HNY2026"
 
-  it should s"send string '$str'" in {
-    simulate(new HNY2026(cfg, str)) { dut =>
+  it should s"send string '$str' in non countinous mode" in {
+    simulate(new HNY2026(cfg.copy(continuous = false), str)) { dut =>
+      enableWaves()
+      dut.clock.step((cfg.clockFreq / cfg.frameRate * cfg.dataWidth * str.length() * 2).toInt)
+      println("See results in the wave diagram.")
+    }
+  }
+
+  it should s"send string '$str' in countinous mode" in {
+    simulate(new HNY2026(cfg.copy(continuous = true), str)) { dut =>
       enableWaves()
       dut.clock.step((cfg.clockFreq / cfg.frameRate * cfg.dataWidth * str.length() * 2).toInt)
       println("See results in the wave diagram.")