From 2821d98c6b7a3061db0bf7f41f14101f80635c22 Mon Sep 17 00:00:00 2001 From: Nikolay Puzanov Date: Thu, 9 Jan 2025 12:54:21 +0300 Subject: [PATCH] Add -O5 option to QuestaSim. Rerun benchmarks. --- README.md | 46 +++++++++++++++++---------------- test-cvc/__build.sh | 2 +- test-cvc/simbench-all.patch | 20 ++++++++++++++ test-cvc/testbench.patch | 16 ++++++------ test-modelsim-O5/.dir-locals.el | 1 + test-modelsim-O5/.gitignore | 2 ++ test-modelsim-O5/__build.sh | 7 +++++ test-modelsim-O5/__run.sh | 5 ++++ test-modelsim-O5/top.sv | 7 +++++ test-modelsim/__run.sh | 2 +- 10 files changed, 76 insertions(+), 32 deletions(-) create mode 100644 test-cvc/simbench-all.patch create mode 100644 test-modelsim-O5/.dir-locals.el create mode 100644 test-modelsim-O5/.gitignore create mode 100755 test-modelsim-O5/__build.sh create mode 100755 test-modelsim-O5/__run.sh create mode 100644 test-modelsim-O5/top.sv diff --git a/README.md b/README.md index 4d6b425..7e5685c 100644 --- a/README.md +++ b/README.md @@ -40,10 +40,12 @@ ## Результаты для 1024 процессоров -- Xeon E5-2630v3 @ 2.40GHz -- Verilator 5.011 devel rev v5.010-98-g15f8ebc56 +- 2 x Xeon E5-2630v3 @ 2.40GHz (no HT), 64GB RAM +- NixOS 24.11 Linux Kernel 6.6.67 + +- GCC 13.3.0 +- Verilator 5.028 2024-08-21 rev v5.028 - Icarus Verilog 13.0 (devel) (s20221226-127-gdeeac2edf) -- ModelSim SE-64 2020.4 (Revision: 2020.10) - QuestaSim 64 2021.1 (Revision: 2021.1) - Vivado 2021.1 - [OSS CVC](https://github.com/cambridgehackers/open-src-cvc) (rev. 782c69a) @@ -52,20 +54,20 @@ ``` | Симулятор | Build | Run | +-----------------------+----------+----------+ -| CVC | 00:02:22 | 00:51:47 | -| Icarus Verilog | 00:00:27 | 19:04:37 | -| ModelSim | 00:00:00 | 01:33:14 | -| QuestaSim | 00:00:00 | 01:29:38 | -| VCS | TBD | | -| Verilator (1 thread) | 00:12:03 | 00:02:57 | -| Verilator (8 threads) | 00:18:45 | 00:01:33 | -| XSIM | 00:00:29 | 02:08:54 | +| CVC | 00:00:05 | 00:57:15 | +| Icarus Verilog | 00:00:23 | 16:15:02 | +| QuestaSim (+acc) | 00:00:00 | 01:06:54 | +| QuestaSim (-O5) | 00:00:00 | 00:06:50 | +| VCS | 00:00:25 | 00:04:12 | +| Verilator (1 thread) | 00:09:23 | 00:02:45 | +| Verilator (8 threads) | 00:09:02 | 00:00:50 | +| XSIM | 00:00:29 | 02:06:16 | | Xcelium | TBD | | ``` -Удалось протестировать Xcelium и VCS на другом оборудованиии и привести время -выполнения бенчмарка к остальным симам. Время сборки на этих симуляторах примерно -соответствует времени сборки на XSIM (Xcelium ближе к Modelsim). +Удалось протестировать Xcelium на другом оборудованиии и привести время выполнения +бенчмарка к остальным симам. Время сборки на этих симуляторах примерно соответствует +времени сборки на XSIM. В таблице ниже показано относительное время выполнения теста, приведенное к времени выполнения на многопоточном Вериляторе. Вериляторы 5.028 и 4.120 показали практически @@ -78,13 +80,13 @@ ``` | Симулятор | Run | +-----------------------+------+ -| CVC | 33 | -| Icarus Verilog | 738 | -| ModelSim | 60 | -| QuestaSim | 58 | -| VCS | 3.8 | -| Verilator (1 thread) | 1.9 | +| CVC | 69 | +| Icarus Verilog | 1170 | +| QuestaSim (+acc) | 80 | +| QuestaSim (-O5) | 8.2 | +| VCS | 5.0 | +| Verilator (1 thread) | 3.3 | | Verilator (8 threads) | 1 | -| XSIM | 83 | -| Xcelium | 4 | +| XSIM | 152 | +| Xcelium | ~4 | ``` diff --git a/test-cvc/__build.sh b/test-cvc/__build.sh index ff46e65..2b7f72b 100755 --- a/test-cvc/__build.sh +++ b/test-cvc/__build.sh @@ -20,6 +20,6 @@ sed -i -e "s/CPU_COUNT = 1024/CPU_COUNT = $CPU_COUNT/" top-mod.sv sources=$(cat $FFILE | grep -v "testbench.sv\|picorv32_tcm.sv") sv2v --top=top -w simbench-all.v top-mod.sv testbench.sv picorv32_tcm.sv $sources -sed -i '1i `timescale 1ps/1ps' simbench-all.v +patch simbench-all.v simbench-all.patch cvc64 -o top -O -pipe +large +nospecify simbench-all.v diff --git a/test-cvc/simbench-all.patch b/test-cvc/simbench-all.patch new file mode 100644 index 0000000..76ea130 --- /dev/null +++ b/test-cvc/simbench-all.patch @@ -0,0 +1,20 @@ +--- simbench-all.v 2025-01-08 22:09:06.737402979 +0300 ++++ simbench-all.v1 2025-01-08 22:08:27.142909974 +0300 +@@ -1,3 +1,4 @@ ++`timescale 1ps/1ps + module top; + parameter CPU_COUNT = 1024; + reg clock = 1'b0; +@@ -13,10 +14,9 @@ + wire [CPU_COUNT - 1:0] done_all; + reg signed [31:0] cycle = 0; + always @(posedge clock) cycle <= cycle + 1; +- genvar _gv_ncpu_1; ++ genvar ncpu; + generate +- for (_gv_ncpu_1 = 0; _gv_ncpu_1 < CPU_COUNT; _gv_ncpu_1 = _gv_ncpu_1 + 1) begin : cpus +- localparam ncpu = _gv_ncpu_1; ++ for (ncpu = 0; ncpu < CPU_COUNT; ncpu = ncpu + 1) begin : cpus + wire done; + reg done_ack = 1'b0; + wire reset; diff --git a/test-cvc/testbench.patch b/test-cvc/testbench.patch index 62cf64a..287e5ec 100644 --- a/test-cvc/testbench.patch +++ b/test-cvc/testbench.patch @@ -1,13 +1,13 @@ diff --git a/source/testbench.sv b/source/testbench.sv -index 1872eed..6f27f84 100644 +index 2949591..084d7a3 100644 --- a/source/testbench.sv +++ b/source/testbench.sv -@@ -32,7 +32,7 @@ module testbench #(parameter CPU_COUNT = 1024) +@@ -34,7 +34,7 @@ module testbench #(parameter CPU_COUNT = 1024) + data_len = DATA_LEN; - initial begin - reset = 1'b1; -- repeat($urandom % 5 + 2) @(posedge clock); -+ repeat($unsigned($random) % 5 + 2) @(posedge clock); - reset = 1'b0; - @(posedge clock); + int reset_duration; +- initial reset_duration = $urandom % CPU_COUNT + 2; ++ initial reset_duration = $unsigned($random) % CPU_COUNT + 2; + assign reset = cycle <= reset_duration; + always @(posedge clock) begin diff --git a/test-modelsim-O5/.dir-locals.el b/test-modelsim-O5/.dir-locals.el new file mode 100644 index 0000000..5621d3a --- /dev/null +++ b/test-modelsim-O5/.dir-locals.el @@ -0,0 +1 @@ +((verilog-mode . ((flycheck-verilator-include-path . ("../source"))))) diff --git a/test-modelsim-O5/.gitignore b/test-modelsim-O5/.gitignore new file mode 100644 index 0000000..f9aacfa --- /dev/null +++ b/test-modelsim-O5/.gitignore @@ -0,0 +1,2 @@ +testbench +transcript diff --git a/test-modelsim-O5/__build.sh b/test-modelsim-O5/__build.sh new file mode 100755 index 0000000..35699ad --- /dev/null +++ b/test-modelsim-O5/__build.sh @@ -0,0 +1,7 @@ +#!/usr/bin/env bash +set -e + +. ../scripts/sim_vars.sh + +rm -rf testbench +vlog -sv -work testbench -vopt $param -f $FFILE top.sv diff --git a/test-modelsim-O5/__run.sh b/test-modelsim-O5/__run.sh new file mode 100755 index 0000000..c284e8b --- /dev/null +++ b/test-modelsim-O5/__run.sh @@ -0,0 +1,5 @@ +#!/usr/bin/env bash + +. ../scripts/sim_vars.sh + +vsim -batch -voptargs=-O5 -do "run -all" -quiet +dlen=$BLOCK_SIZE -GCPU_COUNT=$CPU_COUNT -lib testbench top diff --git a/test-modelsim-O5/top.sv b/test-modelsim-O5/top.sv new file mode 100644 index 0000000..c991b3c --- /dev/null +++ b/test-modelsim-O5/top.sv @@ -0,0 +1,7 @@ +`timescale 1ps/1ps + +module top #(parameter CPU_COUNT = 1024); + logic clock = 1'b0; + initial forever #(10ns/2) clock = ~clock; + testbench #(CPU_COUNT) testbench (clock); +endmodule diff --git a/test-modelsim/__run.sh b/test-modelsim/__run.sh index b7c70f4..3aff5eb 100755 --- a/test-modelsim/__run.sh +++ b/test-modelsim/__run.sh @@ -2,4 +2,4 @@ . ../scripts/sim_vars.sh -vsim -batch -voptargs=+acc=npr -do "run -all" -quiet +dlen=$BLOCK_SIZE -GCPU_COUNT=$CPU_COUNT -lib testbench top +vsim -batch -voptargs="+acc" -do "run -all" -quiet +dlen=$BLOCK_SIZE -GCPU_COUNT=$CPU_COUNT -lib testbench top