From 8b8f63105c287172224cccc451d2736623762fb3 Mon Sep 17 00:00:00 2001 From: Nikolay Puzanov Date: Tue, 11 Jul 2023 19:46:33 +0300 Subject: [PATCH] Add CVC simulator run scripts --- README.md | 3 +++ test-cvc/.dir-locals.el | 1 + test-cvc/.gitignore | 6 ++++++ test-cvc/__build.sh | 25 +++++++++++++++++++++++++ test-cvc/__run.sh | 5 +++++ test-cvc/picorv32_tcm.patch | 18 ++++++++++++++++++ test-cvc/shell.nix | 4 ++++ test-cvc/testbench.patch | 13 +++++++++++++ test-cvc/top.sv | 7 +++++++ 9 files changed, 82 insertions(+) create mode 100644 test-cvc/.dir-locals.el create mode 100644 test-cvc/.gitignore create mode 100755 test-cvc/__build.sh create mode 100755 test-cvc/__run.sh create mode 100644 test-cvc/picorv32_tcm.patch create mode 100644 test-cvc/shell.nix create mode 100644 test-cvc/testbench.patch create mode 100644 test-cvc/top.sv diff --git a/README.md b/README.md index c680569..f3260f2 100644 --- a/README.md +++ b/README.md @@ -46,11 +46,13 @@ - ModelSim SE-64 2020.4 (Revision: 2020.10) - QuestaSim 64 2021.1 (Revision: 2021.1) - Vivado 2021.1 +- [OSS CVC](https://github.com/cambridgehackers/open-src-cvc) (rev. 782c69a) Время выполнения бенчмарка на блоке 1кБ (чч:мм:сс): ``` | Симулятор | Build | Run | +-----------------------+----------+----------+ +| CVC | 00:02:22 | 00:51:47 | | Icarus Verilog | 00:00:27 | 19:04:37 | | ModelSim | 00:00:00 | 01:33:14 | | QuestaSim | 00:00:00 | 01:29:38 | @@ -74,6 +76,7 @@ ``` | Симулятор | Run | +-----------------------+------+ +| CVC | 33 | | Icarus Verilog | 738 | | ModelSim | 60 | | QuestaSim | 58 | diff --git a/test-cvc/.dir-locals.el b/test-cvc/.dir-locals.el new file mode 100644 index 0000000..5621d3a --- /dev/null +++ b/test-cvc/.dir-locals.el @@ -0,0 +1 @@ +((verilog-mode . ((flycheck-verilator-include-path . ("../source"))))) diff --git a/test-cvc/.gitignore b/test-cvc/.gitignore new file mode 100644 index 0000000..0c3d96c --- /dev/null +++ b/test-cvc/.gitignore @@ -0,0 +1,6 @@ +top +picorv32_tcm.sv +simbench-all.v +testbench.sv +top-mod.sv +verilog.log diff --git a/test-cvc/__build.sh b/test-cvc/__build.sh new file mode 100755 index 0000000..ff46e65 --- /dev/null +++ b/test-cvc/__build.sh @@ -0,0 +1,25 @@ +#!/usr/bin/env bash +set -e + +. ../scripts/sim_vars.sh + +rm -rf ./top + +# CVC do not have $urandom function +cp ../source/testbench.sv ./ +patch testbench.sv testbench.patch + +# CVC bug with nonblocking assignment to part of vector +cp ../source/picorv32_tcm.sv ./ +patch picorv32_tcm.sv picorv32_tcm.patch + +# CVC does not support setting parameter via command line +cp ./top.sv ./top-mod.sv +sed -i -e "s/CPU_COUNT = 1024/CPU_COUNT = $CPU_COUNT/" top-mod.sv + +sources=$(cat $FFILE | grep -v "testbench.sv\|picorv32_tcm.sv") + +sv2v --top=top -w simbench-all.v top-mod.sv testbench.sv picorv32_tcm.sv $sources +sed -i '1i `timescale 1ps/1ps' simbench-all.v + +cvc64 -o top -O -pipe +large +nospecify simbench-all.v diff --git a/test-cvc/__run.sh b/test-cvc/__run.sh new file mode 100755 index 0000000..6fd5351 --- /dev/null +++ b/test-cvc/__run.sh @@ -0,0 +1,5 @@ +#!/usr/bin/env bash + +. ../scripts/sim_vars.sh + +./top +dlen=$BLOCK_SIZE diff --git a/test-cvc/picorv32_tcm.patch b/test-cvc/picorv32_tcm.patch new file mode 100644 index 0000000..0cf3ea6 --- /dev/null +++ b/test-cvc/picorv32_tcm.patch @@ -0,0 +1,18 @@ +diff --git a/source/picorv32_tcm.sv b/source/picorv32_tcm.sv +index 29e4d6c..763adc7 100644 +--- a/source/picorv32_tcm.sv ++++ b/source/picorv32_tcm.sv +@@ -39,9 +39,12 @@ module picorv32_tcm #(parameter ADDR_WIDTH = 8, + assign word_addr = byte_addr[ADDR_WIDTH-1:2]; + + always @(posedge clock) begin ++ logic [31:0] tmp; ++ tmp = ram[word_addr]; + for (int n = 0; n < 4; n += 1) + if (write && mem_wstrb[n]) +- ram[word_addr][n*8 +: 8] <= mem_wdata[n*8 +: 8]; ++ tmp[n*8 +: 8] = mem_wdata[n*8 +: 8]; ++ ram[word_addr] <= tmp; + + mem_rdata <= ram[word_addr]; + end diff --git a/test-cvc/shell.nix b/test-cvc/shell.nix new file mode 100644 index 0000000..7610bcd --- /dev/null +++ b/test-cvc/shell.nix @@ -0,0 +1,4 @@ +{ pkgs ? import {} }: + +with pkgs; +mkShell { packages = [ gnumake zlib /* haskellPackages.sv2v */ ]; } diff --git a/test-cvc/testbench.patch b/test-cvc/testbench.patch new file mode 100644 index 0000000..62cf64a --- /dev/null +++ b/test-cvc/testbench.patch @@ -0,0 +1,13 @@ +diff --git a/source/testbench.sv b/source/testbench.sv +index 1872eed..6f27f84 100644 +--- a/source/testbench.sv ++++ b/source/testbench.sv +@@ -32,7 +32,7 @@ module testbench #(parameter CPU_COUNT = 1024) + + initial begin + reset = 1'b1; +- repeat($urandom % 5 + 2) @(posedge clock); ++ repeat($unsigned($random) % 5 + 2) @(posedge clock); + reset = 1'b0; + @(posedge clock); + diff --git a/test-cvc/top.sv b/test-cvc/top.sv new file mode 100644 index 0000000..fcb67d9 --- /dev/null +++ b/test-cvc/top.sv @@ -0,0 +1,7 @@ +`timescale 1ps/1ps + +module top #(parameter CPU_COUNT = 1024); + logic clock = 1'b0; + initial forever #5000 clock = ~clock; + testbench #(CPU_COUNT) testbench (clock); +endmodule