From c277e3482ac519e57f19e8eab063f7f4fb0b6e07 Mon Sep 17 00:00:00 2001 From: Nikolay Puzanov Date: Wed, 2 Oct 2024 17:25:04 +0300 Subject: [PATCH] Add old (without --timing) verilator test --- README.md | 4 +- source/md5calculator.sv | 14 +++---- source/testbench.sv | 37 ++++++++++--------- .../.clang-format | 0 .../.gitignore | 0 {test-verilator => test-verilator4}/Makefile | 4 +- .../__build.sh | 0 {test-verilator => test-verilator4}/__run.sh | 0 .../clock_generator.cpp | 0 .../clock_generator.hpp | 0 {test-verilator => test-verilator4}/shell.nix | 0 {test-verilator => test-verilator4}/top.cpp | 0 test-verilator5/.gitignore | 1 + test-verilator5/Makefile | 19 ++++++++++ test-verilator5/__build.sh | 7 ++++ test-verilator5/__run.sh | 5 +++ test-verilator5/top.sv | 7 ++++ 17 files changed, 70 insertions(+), 28 deletions(-) rename {test-verilator => test-verilator4}/.clang-format (100%) rename {test-verilator => test-verilator4}/.gitignore (100%) rename {test-verilator => test-verilator4}/Makefile (71%) rename {test-verilator => test-verilator4}/__build.sh (100%) rename {test-verilator => test-verilator4}/__run.sh (100%) rename {test-verilator => test-verilator4}/clock_generator.cpp (100%) rename {test-verilator => test-verilator4}/clock_generator.hpp (100%) rename {test-verilator => test-verilator4}/shell.nix (100%) rename {test-verilator => test-verilator4}/top.cpp (100%) create mode 100644 test-verilator5/.gitignore create mode 100644 test-verilator5/Makefile create mode 100755 test-verilator5/__build.sh create mode 100755 test-verilator5/__run.sh create mode 100644 test-verilator5/top.sv diff --git a/README.md b/README.md index f3260f2..4d6b425 100644 --- a/README.md +++ b/README.md @@ -68,7 +68,9 @@ соответствует времени сборки на XSIM (Xcelium ближе к Modelsim). В таблице ниже показано относительное время выполнения теста, приведенное к времени -выполнения на многопоточном Вериляторе. +выполнения на многопоточном Вериляторе. Вериляторы 5.028 и 4.120 показали практически +одинаковую скорость, разность в пределах погрешности. Но в 5.028 была включена опция +`--timing`, а клок формировался в верилоге. "По просьбе выживших, имена были изменены. Из уважения к погибшим, остальное было рассказано в точности так, как это произошло." diff --git a/source/md5calculator.sv b/source/md5calculator.sv index b0988d5..74762ff 100644 --- a/source/md5calculator.sv +++ b/source/md5calculator.sv @@ -216,13 +216,11 @@ module md5calculator ); // Print console output - initial - forever begin - @(posedge clock); - if (!reset && console_send) begin - $write("%c", o_console_data); - $fflush; - end - end + always @(posedge clock) begin + if (!reset && console_send) begin + $write("%c", o_console_data); + $fflush; + end + end endmodule // testbench diff --git a/source/testbench.sv b/source/testbench.sv index 1872eed..2949591 100644 --- a/source/testbench.sv +++ b/source/testbench.sv @@ -9,8 +9,11 @@ module testbench #(parameter CPU_COUNT = 1024) logic [31:0] data_len; logic [CPU_COUNT-1:0] done_all; + int cycle = 0; + always @(posedge clock) cycle <= cycle + 1; + for (genvar ncpu = 0; ncpu < CPU_COUNT; ncpu = ncpu + 1) begin : cpus - logic done; + logic done, done_ack = 1'b0; logic reset; logic [127:0] md5; @@ -30,27 +33,27 @@ module testbench #(parameter CPU_COUNT = 1024) if(!$value$plusargs("dlen=%d", data_len)) data_len = DATA_LEN; - initial begin - reset = 1'b1; - repeat($urandom % 5 + 2) @(posedge clock); - reset = 1'b0; - @(posedge clock); + int reset_duration; + initial reset_duration = $urandom % CPU_COUNT + 2; + assign reset = cycle <= reset_duration; - while(!done) @(posedge clock); - $display("MD5(0x%x) = %x", ncpu, md5); + always @(posedge clock) begin + if (cycle > reset_duration && done && !done_ack) begin + done_ack <= 1'b1; + $display("MD5(0x%x) = %x", ncpu, md5); + end end end // Wait for complete - initial begin - $display("--- BENCH BEGIN ---"); - - repeat(5) @(posedge clock); - while ((&done_all) == 1'b0) @(posedge clock); - @(posedge clock); - - $display("--- BENCH DONE ---"); - $finish; + always @(posedge clock) begin + if (cycle == 0) $display("--- BENCH BEGIN ---"); + else if (cycle > 5) begin + if (&done_all) begin + $display("--- BENCH DONE ---"); + $finish; + end + end end endmodule // testbench diff --git a/test-verilator/.clang-format b/test-verilator4/.clang-format similarity index 100% rename from test-verilator/.clang-format rename to test-verilator4/.clang-format diff --git a/test-verilator/.gitignore b/test-verilator4/.gitignore similarity index 100% rename from test-verilator/.gitignore rename to test-verilator4/.gitignore diff --git a/test-verilator/Makefile b/test-verilator4/Makefile similarity index 71% rename from test-verilator/Makefile rename to test-verilator4/Makefile index ddf8d36..3feef7e 100644 --- a/test-verilator/Makefile +++ b/test-verilator4/Makefile @@ -7,8 +7,8 @@ PARAMS := THREADS := 1 FLAGS = -Wno-WIDTH -cc --top-module $(TOP_MODULE) +1800-2017ext+sv \ - --timing --Mdir $(TOP_MODULE) -o $(TOP_MODULE) -f $(FLAGS_FILE) \ - $(PARAMS) --timescale "1ps/1ps" --threads $(THREADS) -j 0 + --Mdir $(TOP_MODULE) -o $(TOP_MODULE) -f $(FLAGS_FILE) \ + $(PARAMS) --timescale "1ps/1ps" --threads $(THREADS) -j 16 # FLAGS += --trace diff --git a/test-verilator/__build.sh b/test-verilator4/__build.sh similarity index 100% rename from test-verilator/__build.sh rename to test-verilator4/__build.sh diff --git a/test-verilator/__run.sh b/test-verilator4/__run.sh similarity index 100% rename from test-verilator/__run.sh rename to test-verilator4/__run.sh diff --git a/test-verilator/clock_generator.cpp b/test-verilator4/clock_generator.cpp similarity index 100% rename from test-verilator/clock_generator.cpp rename to test-verilator4/clock_generator.cpp diff --git a/test-verilator/clock_generator.hpp b/test-verilator4/clock_generator.hpp similarity index 100% rename from test-verilator/clock_generator.hpp rename to test-verilator4/clock_generator.hpp diff --git a/test-verilator/shell.nix b/test-verilator4/shell.nix similarity index 100% rename from test-verilator/shell.nix rename to test-verilator4/shell.nix diff --git a/test-verilator/top.cpp b/test-verilator4/top.cpp similarity index 100% rename from test-verilator/top.cpp rename to test-verilator4/top.cpp diff --git a/test-verilator5/.gitignore b/test-verilator5/.gitignore new file mode 100644 index 0000000..bf1a1fd --- /dev/null +++ b/test-verilator5/.gitignore @@ -0,0 +1 @@ +top diff --git a/test-verilator5/Makefile b/test-verilator5/Makefile new file mode 100644 index 0000000..3e8cfee --- /dev/null +++ b/test-verilator5/Makefile @@ -0,0 +1,19 @@ +TOP_MODULE = top + +SOURCES = top.sv +FLAGS_FILE = ../source/sources.f +INCLUDES = +PARAMS := +THREADS := 1 + +FLAGS = -Wno-WIDTH --top-module $(TOP_MODULE) +1800-2017ext+sv \ + --timing --Mdir $(TOP_MODULE) -o $(TOP_MODULE) -f $(FLAGS_FILE) \ + $(PARAMS) --timescale "1ps/1ps" --threads $(THREADS) -j 0 + +# FLAGS += --trace + +all: $(SOURCES) + verilator $(FLAGS) --binary $(INCLUDES) $(SOURCES) + +clean: + rm -rf $(TOP_MODULE) diff --git a/test-verilator5/__build.sh b/test-verilator5/__build.sh new file mode 100755 index 0000000..cdc3454 --- /dev/null +++ b/test-verilator5/__build.sh @@ -0,0 +1,7 @@ +#!/usr/bin/env bash +set -e + +. ../scripts/sim_vars.sh + +make clean +make OPT_FAST="-Os -march=native" VM_PARALLEL_BUILDS=0 PARAMS="-GCPU_COUNT=$CPU_COUNT" THREADS=$THREADS diff --git a/test-verilator5/__run.sh b/test-verilator5/__run.sh new file mode 100755 index 0000000..f03b975 --- /dev/null +++ b/test-verilator5/__run.sh @@ -0,0 +1,5 @@ +#!/usr/bin/env bash + +. ../scripts/sim_vars.sh + +./top/top +dlen=$BLOCK_SIZE diff --git a/test-verilator5/top.sv b/test-verilator5/top.sv new file mode 100644 index 0000000..ec2f25f --- /dev/null +++ b/test-verilator5/top.sv @@ -0,0 +1,7 @@ +`timescale 1ps/1ps + +module top #(parameter CPU_COUNT = 2); + logic clock = 1'b0; + initial forever #(10ns/2) clock = ~clock; + testbench #(CPU_COUNT) testbench (clock); +endmodule