# verilog-align

Align SystemVerilog port declarations, instantiations, and signal declarations around point.

## Features

- Aligns direction, type, range, name, and trailing `//` comments.
- Works on the contiguous block of port declarations above and below point.
- Stops at the first non-port line (including blank lines).
- Aligns named port connections in module instantiations via `verilog-align-instantiation`.
- Aligns signal declarations via `verilog-align-declarations`.

## Installation

```elisp
(add-to-list 'load-path "/path/to/verilog-align")
(require 'verilog-align)
```

## Usage

1. Place point on a line that declares a port (input/output/inout).
2. Run `M-x verilog-align-ports`.

For module instantiations:

1. Place point on a named port connection line (e.g., `.clk_i (clk)` or `.full_o,`).
2. Run `M-x verilog-align-instantiation`.

For signal declarations:

1. Place point on a declaration line (e.g., `logic foo;` or `wire [3:0] bar;`).
2. Run `M-x verilog-align-declarations`.

Example input:

```systemverilog
  input wire rst_i, // rst,
  input wire clk_i, // wr_clk,
  input wire [DataWidth-1:0] d_i, // din,
  output logic full_o,  // full,
  output [DataWidth-1:0]   d_o, // dout,
  output empty_o,// empty,
  output logic valid_o    // data_valid
```

Example output:

```systemverilog
  input  wire                  rst_i,   // rst,
  input  wire                  clk_i,   // wr_clk,
  input  wire  [DataWidth-1:0] d_i,     // din,
  output logic                 full_o,  // full,
  output       [DataWidth-1:0] d_o,     // dout,
  output                       empty_o, // empty,
  output logic                 valid_o  // data_valid
```

## Tests

Run:

```bash
./run-tests.sh
```