;;; verilog-align-test.el --- Tests for verilog-align -*- lexical-binding: t; -*-

;;; Commentary:
;; ERT tests for verilog-align.

;;; Code:

(require 'ert)

(defconst verilog-align-test--dir
  (file-name-directory (or load-file-name buffer-file-name)))

(load-file (expand-file-name "verilog-align.el"
                             verilog-align-test--dir))

(ert-deftest verilog-align-ports-aligns-block ()
  (let* ((input (concat
                 (mapconcat
                  #'identity
                  '("module fifo_sync #("
                    "  parameter integer FifoWriteDepth   = 2048,"
                    "  parameter integer DataWidth        = 32,"
                    "  parameter integer WrDataCountWidth = $clog2(FifoWriteDepth)+1,"
                    "  parameter integer RdDataCountWidth = 4"
                    ") ("
                    "  input wire rst_i, // rst,"
                    "  input wire clk_i, // wr_clk,"
                    "  input wire wr_en_i, // wr_en,"
                    "  input wire [DataWidth-1:0] d_i, // din,"
                    "  output logic full_o,  // full,"
                    "  output logic [WrDataCountWidth-1:0] wr_data_count_o, // wr_data_count,"
                    "  input wire rd_en_i, // rd_en,"
                    "  output [DataWidth-1:0]   d_o, // dout,"
                    "  output empty_o,// empty,"
                    "  output logic valid_o    // data_valid"
                    ");")
                  "\n")
                 "\n"))
         (expected (concat
                    (mapconcat
                     #'identity
                     '("module fifo_sync #("
                       "  parameter integer FifoWriteDepth   = 2048,"
                       "  parameter integer DataWidth        = 32,"
                       "  parameter integer WrDataCountWidth = $clog2(FifoWriteDepth)+1,"
                       "  parameter integer RdDataCountWidth = 4"
                       ") ("
                       "  input  wire                         rst_i,           // rst,"
                       "  input  wire                         clk_i,           // wr_clk,"
                       "  input  wire                         wr_en_i,         // wr_en,"
                       "  input  wire  [DataWidth-1:0]        d_i,             // din,"
                       "  output logic                        full_o,          // full,"
                       "  output logic [WrDataCountWidth-1:0] wr_data_count_o, // wr_data_count,"
                       "  input  wire                         rd_en_i,         // rd_en,"
                       "  output       [DataWidth-1:0]        d_o,             // dout,"
                       "  output                              empty_o,         // empty,"
                       "  output logic                        valid_o          // data_valid"
                       ");")
                     "\n")
                    "\n")))
    (with-temp-buffer
      (insert input)
      (goto-char (point-min))
      (search-forward "input wire clk_i")
      (beginning-of-line)
      (verilog-align-ports)
      (should (string= (buffer-string) expected)))))

(ert-deftest verilog-align-instantiation-aligns-block ()
  (let* ((input (concat
                 (mapconcat
                  #'identity
                  '("fifo_sync #("
                    "  .FifoWriteDepth(FifoWriteDepth),"
                    "  .DataWidth(DataWidth),"
                    "  .DataCountWidth(WrDataCountW),"
                    "  .RdDataCountWidth(RdDataCountW)"
                    ") dut ("
                    "  .rst_i (rst),  //rst"
                    "  .clk_i     (clk),"
                    "  .wr_en_i            (wr_en_i),"
                    "  .d_i          (d_i),  // di"
                    "  .full_o,      // full"
                    "  .data_count_o (wr_data_count_o),"
                    "  .rd_en_i   (rd_en_i),"
                    "  .d_o      ()  , // do"
                    "  .empty_o , // empty"
                    "  .valid_o         (valid_o)"
                    ");")
                  "\n")
                 "\n"))
         (expected (concat
                    (mapconcat
                     #'identity
                     (list
                      "fifo_sync #("
                      "  .FifoWriteDepth(FifoWriteDepth),"
                      "  .DataWidth(DataWidth),"
                      "  .DataCountWidth(WrDataCountW),"
                      "  .RdDataCountWidth(RdDataCountW)"
                      ") dut ("
                      (concat "  .rst_i" (make-string 8 ?\s) "(rst),"
                              (make-string 13 ?\s) "//rst")
                      (concat "  .clk_i" (make-string 8 ?\s) "(clk),")
                      (concat "  .wr_en_i" (make-string 6 ?\s) "(wr_en_i),")
                      (concat "  .d_i" (make-string 10 ?\s) "(d_i),"
                              (make-string 13 ?\s) "// di")
                      (concat "  .full_o," (make-string 25 ?\s) "// full")
                      (concat "  .data_count_o" (make-string 1 ?\s)
                              "(wr_data_count_o),")
                      (concat "  .rd_en_i" (make-string 6 ?\s) "(rd_en_i),")
                      (concat "  .d_o" (make-string 10 ?\s) "(),"
                              (make-string 16 ?\s) "// do")
                      (concat "  .empty_o," (make-string 24 ?\s) "// empty")
                      (concat "  .valid_o" (make-string 6 ?\s) "(valid_o)")
                      ");")
                     "\n")
                    "\n")))
    (with-temp-buffer
      (insert input)
      (goto-char (point-min))
      (search-forward ".clk_i")
      (beginning-of-line)
      (should (verilog-align-instantiation))
      (should (string= (buffer-string) expected)))))

(ert-deftest verilog-align-instantiation-returns-nil-outside ()
  (with-temp-buffer
    (insert (concat
             (mapconcat
              #'identity
              '("fifo_sync #() dut ("
                "  .rst_i (rst),"
                "  .clk_i (clk)"
                ");")
              "\n")
             "\n"))
    (goto-char (point-min))
    (search-forward "dut (")
    (beginning-of-line)
    (should (not (verilog-align-instantiation)))))

(ert-deftest verilog-align-declarations-aligns-block ()
  (let* ((input (concat
                 (mapconcat
                  #'identity
                  '("logic  wr_en_i;   // write enable"
                    "logic [DataWidth-1:0]    d_i;   // data input"
                    "logic full_o;"
                    "logic [WrDataCountW-1:0] wr_data_count_o; // data count"
                    "wire   rd_en_i; // read enable"
                    "logic [DataWidth-1:0]    d_o;"
                    "reg empty_o;// empty flag"
                    "logic valid_o;")
                  "\n")
                 "\n"))
         (expected (concat
                    (mapconcat
                     #'identity
                     (list
                      (concat "logic" (make-string 20 ?\s)
                              "wr_en_i;" (make-string 9 ?\s)
                              "// write enable")
                      (concat "logic" " " "[DataWidth-1:0]" (make-string 4 ?\s)
                              "d_i;" (make-string 13 ?\s)
                              "// data input")
                      (concat "logic" (make-string 20 ?\s) "full_o;")
                      (concat "logic" " " "[WrDataCountW-1:0]" " "
                              "wr_data_count_o;" " " "// data count")
                      (concat "wire" (make-string 21 ?\s)
                              "rd_en_i;" (make-string 9 ?\s)
                              "// read enable")
                      (concat "logic" " " "[DataWidth-1:0]" (make-string 4 ?\s)
                              "d_o;")
                      (concat "reg" (make-string 22 ?\s)
                              "empty_o;" (make-string 9 ?\s)
                              "// empty flag")
                      (concat "logic" (make-string 20 ?\s) "valid_o;")
                      )
                     "\n")
                    "\n")))
    (with-temp-buffer
      (insert input)
      (goto-char (point-min))
      (search-forward "logic full_o")
      (beginning-of-line)
      (should (verilog-align-declarations))
      (should (string= (buffer-string) expected)))))

(ert-deftest verilog-align-declarations-returns-nil-outside ()
  (with-temp-buffer
    (insert (concat
             (mapconcat
              #'identity
              '("module foo;"
                "logic a;"
                "endmodule")
              "\n")
             "\n"))
    (goto-char (point-min))
    (search-forward "module foo")
    (beginning-of-line)
    (should (not (verilog-align-declarations)))))

(provide 'verilog-align-test)

;;; verilog-align-test.el ends here