diff --git a/_template_verilator/top.sv b/_template_verilator/top.sv
index 2744f99..5c51626 100644
--- a/_template_verilator/top.sv
+++ b/_template_verilator/top.sv
@@ -1,11 +1,5 @@
 `timescale 1ps/1ps
 
-/* -verilator lint_off DECLFILENAME */
-/* -verilator lint_off MULTITOP */
-/* -verilator lint_off STMTDLY */
-/* -verilator lint_off INFINITELOOP */
-/* -verilator lint_off INITIALDLY */
-
 module top
   (input wire clock,
    input wire reset);