From 54f7e2be54481c533148a5bb9234e0c171c86031 Mon Sep 17 00:00:00 2001
From: Nikolay Puzanov <np@embddr.com>
Date: Tue, 13 Dec 2022 11:49:15 +0300
Subject: [PATCH] Enable trace of structs

---
 _web_server/server/playground-server.scm | 50 ++++++++++++++++++------
 _web_server/server/top_iverilog.sv       |  2 +-
 2 files changed, 40 insertions(+), 12 deletions(-)

diff --git a/_web_server/server/playground-server.scm b/_web_server/server/playground-server.scm
index 9ae21c0..02ef2af 100755
--- a/_web_server/server/playground-server.scm
+++ b/_web_server/server/playground-server.scm
@@ -319,14 +319,40 @@
 ;;; Make legend SVG text for VCD
 ;;;
 (define* (vcd-signals->legend signals text-spacing text-position)
-  (map
-   (lambda (sig n)
-     (string-append
-      (format-inex "<text x=\"0\" y=\"~a\">~a</text>"
-                   (+ (* n text-spacing) text-position)
-                   (vcd-signal-name sig))))
-   signals
-   (iota (length signals))))
+  (if (null? signals)
+      ""
+      (let ((common-scope-len
+             (length
+              (fold
+               (lambda (scope common)
+                 (let loop ((scope scope)
+                            (common common)
+                            (out '()))
+                   (if (or (null? scope)
+                           (null? common))
+                       (reverse out)
+                       (if (string-ci= (car scope)
+                                       (car common))
+                           (loop (cdr scope)
+                                 (cdr common)
+                                 (cons (car scope) out))
+                           (reverse out)))))
+               (vcd-signal-scope (car signals))
+               (map vcd-signal-scope (cdr signals))))))
+        (map
+         (lambda (sig n)
+           (string-append
+            (format-inex "<text x=\"0\" y=\"~a\">~a</text>"
+                         (+ (* n text-spacing) text-position)
+                         (string-concatenate
+                          (insert-between
+                           (append
+                            (drop (vcd-signal-scope sig)
+                                  common-scope-len)
+                            `(,(vcd-signal-name sig)))
+                           ".")))))
+         signals
+         (iota (length signals))))))
 
 ;;;
 ;;; Create SVG from VCD
@@ -336,7 +362,7 @@
                    (signal-text-position 12)
                    (margin 5)
                    (signal-spacing 5)
-                   (legend-width 100)
+                   (legend-width 150)
                    (extra-delim-y 3))
 
   (let ((tstart (apply min (vcd-timestamps vcd)))
@@ -556,6 +582,8 @@
           (println "+1800-2017ext+sv")
           (println "--timing")
           (println "--trace")
+          (println "--trace-structs")
+          (println "--trace-depth 1")
           (println "--quiet-exit")
           (println "~a" verilog-file)
           (println "~a.cpp" top))))
@@ -610,7 +638,7 @@
           (values status log (vcd-file-read
                               vcd-file
                               (lambda (sig)
-                                (= 2 (length (vcd-signal-scope sig))))))
+                                (>= (length (vcd-signal-scope sig)) 2))))
           (values status log #f)))))
 
 ;;;
@@ -632,7 +660,7 @@
           (values status log (vcd-file-read
                               vcd-file
                               (lambda (sig)
-                                (= 2 (length (vcd-signal-scope sig))))))
+                                (>= (length (vcd-signal-scope sig)) 2))))
           (values status log #f)))))
 
 ;;;
diff --git a/_web_server/server/top_iverilog.sv b/_web_server/server/top_iverilog.sv
index 00803c2..9dcada1 100644
--- a/_web_server/server/top_iverilog.sv
+++ b/_web_server/server/top_iverilog.sv
@@ -6,7 +6,7 @@ module __@TOPMODULE@__;
     @TOPMODULE@ @TOPMODULE@ (clock);
     initial begin
         $dumpfile("@WORKDIR@/@TOPMODULE@.vcd");
-        $dumpvars(0, @TOPMODULE@);
+        $dumpvars(1, @TOPMODULE@);
         $dumplimit(100000);
     end
 endmodule