From 838bbac6451de5088c00394d0278acb80c139145 Mon Sep 17 00:00:00 2001
From: Nikolay Puzanov <np@embddr.com>
Date: Mon, 21 Nov 2022 20:57:43 +0300
Subject: [PATCH] Verilator: Generate correct reset

---
 _template_verilator/top.cpp | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/_template_verilator/top.cpp b/_template_verilator/top.cpp
index c50c9a5..5654cdc 100644
--- a/_template_verilator/top.cpp
+++ b/_template_verilator/top.cpp
@@ -30,7 +30,10 @@ int main(int argc, char **argv)
     clk->next_event();
 
     /* Initial */
-    top->reset = 0;
+    top->reset = 1;
+
+    /* Cycle counter */
+    uint64_t cycle = 0;
 
     /* ---- Evaluation loop ---- */
     while (!ctx->gotFinish()) {
@@ -47,13 +50,15 @@ int main(int argc, char **argv)
 
         /* Put input values (after clock edge)*/
         if (clk->is_posegde(top->clock)) {
-            top->reset = !top->reset;
+            top->reset = (cycle < 5) ? 1 : 0;
         }
 
         /* Trace steady-state values */
 #if (VM_TRACE == 1)
         if (vcd) vcd->dump(ctx->time());
 #endif
+
+        cycle ++;
     }
 
     top->final();