From cc605cce85ac05c5746d2bfbd097c4eb60e6cfa8 Mon Sep 17 00:00:00 2001 From: Nikolay Puzanov Date: Fri, 9 Dec 2022 10:21:40 +0300 Subject: [PATCH] Top module for all simulators must have an input clock signal --- _web_server/server/playground-server.scm | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/_web_server/server/playground-server.scm b/_web_server/server/playground-server.scm index 13f48f5..9ae21c0 100755 --- a/_web_server/server/playground-server.scm +++ b/_web_server/server/playground-server.scm @@ -794,7 +794,7 @@ "Rules:" "0. Don't fool around ;)" "1. The top module must be named 'testbench'." - "2. The top module for the Verilator must have an input clock signal." + "2. The top module must have an input clock signal." "3. Code size should not exceed 10000 characters." "4. Code execution time no longer than 5 seconds.") "\\n"))))))