TOP_MODULE = top

SOURCES = top.sv top.cpp clock_generator.cpp
INCLUDES =

## Parameters example:
# PARAM_INPUT_WIDTH ?= 15
# PARAM_FFT_LENGTH ?= 256
# PARAM_REJECTOR_K_WIDTH ?= 8

FLAGS = -Wno-WIDTH -cc --top-module $(TOP_MODULE) +1800-2017ext+sv \
	--timing --trace --Mdir $(TOP_MODULE) -o $(TOP_MODULE)
FLAGS += $(foreach V,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(V))=$($(V)))

all: $(SOURCES)
	verilator $(FLAGS) --exe --build $(INCLUDES) $(SOURCES)

pre:
	verilator $(FLAGS) $(INCLUDES) $(SOURCES)

clean:
	rm -rf $(TOP_MODULE)
	rm -rf *.vcd