`timescale 1ps/1ps

/* -verilator lint_off DECLFILENAME */
/* -verilator lint_off MULTITOP */
/* -verilator lint_off STMTDLY */
/* -verilator lint_off INFINITELOOP */
/* -verilator lint_off INITIALDLY */

module top
  (input wire clock,
   input wire reset);

    initial begin
        for (int n = 0; n < 10; n += 1) begin
            $display("R@%0t: %0b\n", $time, reset);
            @(posedge clock);
        end

        $finish;
    end

endmodule // top