Add additional verilog defines UTEST_*
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parent
b5d2b12863
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24
utest.scm
24
utest.scm
@ -528,6 +528,24 @@
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((find (lambda (x) (string-prefix? sim-warn-prefix x)) log) 'warning)
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((find (lambda (x) (string-prefix? sim-warn-prefix x)) log) 'warning)
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(else #t))))
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(else #t))))
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;;;
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;;; Return list of UTEST_* defines
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;;;
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(define (utest-verilog-defines)
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(append
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`((UTEST_BASE_DIR ,(format "'\"~a\"'" (utest/base-path)))
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(UTEST_WORK_DIR ,(format "'\"~a\"'" (utest/work-path))))
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(fold (lambda (x l)
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(if (car x)
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(append l (cdr x))
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l))
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'()
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`((,(utest/verbose) UTEST_VERBOSE)
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(,(utest/force-dump) UTEST_FORCE_DUMP)
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(,(utest/keep-output) UTEST_KEEP_OUTPUT)
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(,(utest/restart-dump) UTEST_RESTART_DUMP)))))
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;;;
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;;;
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;;; Run compile and simulation with Icarus Verilog
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;;; Run compile and simulation with Icarus Verilog
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;;;
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;;;
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@ -564,11 +582,7 @@
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(let ((sources (append (map (lambda (x) (path->absolute x base-path))
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(let ((sources (append (map (lambda (x) (path->absolute x base-path))
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(arg-to-list sources))
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(arg-to-list sources))
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(list timeout-module dump-module)))
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(list timeout-module dump-module)))
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(defines (append defines (utest-verilog-defines)))
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(defines (append defines
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`((UTEST_BASE_DIR ,(format "'\"~a\"'" base-path))
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(UTEST_WORK_DIR ,(format "'\"~a\"'" work-path)))))
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(includes (append (map (lambda (x) (path->absolute x base-path)) (arg-to-list includes))
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(includes (append (map (lambda (x) (path->absolute x base-path)) (arg-to-list includes))
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(list base-path)))
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(list base-path)))
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