23 lines
438 B
Systemverilog
23 lines
438 B
Systemverilog
`timescale 1ps/1ps
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`include "utest.vh"
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module vpi_log2 #(parameter ARGUMENT = 1.0,
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parameter SIGMA = 1e-6);
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real dut, gold;
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initial begin
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gold = $ln(ARGUMENT) / $ln(2);
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dut = $log2(ARGUMENT);
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`log_info(("Gold: %0f", gold));
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`log_info((" DUT: %0f", dut));
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if ($abs(gold - dut) > SIGMA)
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`log_error(("FAIL"));
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$finish;
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end
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endmodule // vpi_log2
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