Initial commit

tangNano1k/resources/hny2026.cst

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+//Copyright (C)2014-2021 Gowin Semiconductor Corporation.
+//All rights reserved. 
+//File Title: Physical Constraints file
+//GOWIN Version: 1.9.8
+//Part Number: GW1NZ-LV1QN48C6/I5
+//Device: GW1NZ-1
+//Created Time: Thu 09 16 14:45:08 2021
+
+IO_LOC "led[2]" 11;
+IO_PORT "led[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8;
+IO_LOC "led[1]" 10;
+IO_PORT "led[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8;
+IO_LOC "led[0]" 9;
+IO_PORT "led[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8;
+IO_LOC "sys_rst_n" 13;
+IO_PORT "sys_rst_n" IO_TYPE=LVCMOS33 PULL_MODE=UP;
+IO_LOC "sys_clk" 47;
+IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=UP;

tangNano1k/verilog/hny2026_top.v

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+// %SOURCE_FILE_HEADER%
+//
+
+module hny2026_top (
+    input wire sys_clk,
+    input wire sys_rst_n,
+    // 0 - R, 1 - B, 2 - G
+    output wire [2:0] led
+);
+
+    reg [2:0] rst_sync;
+    wire reset = ~rst_sync[0];
+    always @(posedge sys_clk) rst_sync <= {sys_rst_n, rst_sync[2:1]};
+
+    wire [2:0] led_inv;
+    assign led = ~led_inv;
+
+    HNY2026 hny2026 (
+        .clock(sys_clk),
+        .reset(reset),
+        .io_ledR(led_inv[0]),
+        .io_ledG(led_inv[2]),
+        .io_ledB(led_inv[1])
+    );
+
+endmodule // hny2026_top