Add VCS and Xcelium run time. Fix RTL for VCS to work correctly

README.md

@@ -49,13 +49,33 @@
 
 Время выполнения бенчмарка на блоке 1кБ (чч:мм:сс):
 ```
-  | Симулятор             | Build    | Run      |
-  +-----------------------+----------+----------+
-  | Icarus Verilog        | 00:00:27 | 19:04:37 |
-  | ModelSim              | 00:00:00 | 01:33:14 |
-  | QuestaSim             | 00:00:00 | 01:29:38 |
-  | Verilator (1 thread)  | 00:12:03 | 00:02:57 |
-  | Verilator (8 threads) | 00:18:45 | 00:01:33 |
-  | XSIM                  | 00:00:29 | 02:08:54 |
-  | Xcelium               | TBD      |          |
+| Симулятор             | Build    | Run      |
++-----------------------+----------+----------+
+| Icarus Verilog        | 00:00:27 | 19:04:37 |
+| ModelSim              | 00:00:00 | 01:33:14 |
+| QuestaSim             | 00:00:00 | 01:29:38 |
+| VCS                   | TBD      |          |
+| Verilator (1 thread)  | 00:12:03 | 00:02:57 |
+| Verilator (8 threads) | 00:18:45 | 00:01:33 |
+| XSIM                  | 00:00:29 | 02:08:54 |
+| Xcelium               | TBD      |          |
+```
+
+Удалось протестировать Xcelium и VCS на другом оборудованиии и привести время
+выполнения бенчмарка к остальным симам.
+
+"По просьбе выживших, имена были изменены. Из уважения к погибшим, остальное было
+рассказано в точности так, как это произошло."
+
+```
+| Симулятор             | Build  | Run  |
++-----------------------+--------+------+
+| Icarus Verilog        |      1 |  738 |
+| ModelSim              |      0 |   60 |
+| QuestaSim             |      0 |   58 |
+| VCS                   |      1 |  3.8 |
+| Verilator (1 thread)  |     26 |  1.9 |
+| Verilator (8 threads) |     40 |    1 |
+| XSIM                  |      1 |   83 |
+| Xcelium               |    0.2 |    4 |
 ```

source/picorv32_tcm.sv

@@ -38,7 +38,7 @@ module picorv32_tcm #(parameter ADDR_WIDTH = 8,
 
     assign word_addr = byte_addr[ADDR_WIDTH-1:2];
 
-    always_ff @(posedge clock) begin
+    always @(posedge clock) begin
         for (int n = 0; n < 4; n += 1)
           if (write && mem_wstrb[n])
             ram[word_addr][n*8 +: 8] <= mem_wdata[n*8 +: 8];

test-vcs/.dir-locals.el

@@ -0,0 +1 @@
+((verilog-mode . ((flycheck-verilator-include-path . ("../source")))))

test-vcs/__build.sh

@@ -0,0 +1,8 @@
+#!/usr/bin/env bash
+set -e
+
+. ../scripts/sim_vars.sh
+
+rm -rf csrc simv.daidir simv
+
+vcs -full64 -lca -sverilog -notice -nc -timescale=1ns/1ps -f $FFILE -pvalue+top.CPU_COUNT=$CPU_COUNT -l build.log top.sv

test-vcs/__run.sh

@@ -0,0 +1,5 @@
+#!/usr/bin/env bash
+
+. ../scripts/sim_vars.sh
+
+./simv +dlen=$BLOCK_SIZE

test-vcs/top.sv

@@ -0,0 +1,7 @@
+`timescale 1ps/1ps
+
+module top #(parameter CPU_COUNT = 1024);
+    logic clock = 1'b0;
+    initial forever #(10ns/2) clock = ~clock;
+    testbench #(CPU_COUNT) testbench (clock);
+endmodule