Add sources

test-modelsim/.dir-locals.el

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+((verilog-mode . ((flycheck-verilator-include-path . ("../source")))))

test-modelsim/.gitignore

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+testbench
+transcript

test-modelsim/__build.sh

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+#!/usr/bin/env bash
+set -e
+
+rm -rf testbench
+vlog -sv -work testbench -vopt -f ../source/sources.f top.sv

test-modelsim/__run.sh

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+#!/usr/bin/env bash
+
+vsim -c -batch -voptargs=+acc=npr -do "run -all" -quiet -lib testbench top

test-modelsim/top.sv

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+`timescale 1ps/1ps
+
+module top;
+    logic clock = 1'b0;
+    initial forever #(10ns/2) clock = ~clock;
+    testbench testbench (clock);
+endmodule