Set block size to 1kB. Block size is set via plusarg +dlen=NNN

README.md

@@ -2,7 +2,9 @@
 
 Для оценки скорости запускается симуляция 1024 софт-процессоров
 [PicoRV32](https://github.com/YosysHQ/picorv32) с программой вычисления хэш-суммы MD5
-от блока 64кБ. Данные в каждом блоке инициализируются разными значениями.
+от блока 1кБ. Данные в каждом блоке инициализируются разными значениями. Размер блока
+по-усолчанию равен 1кБ, но с помощью параметра `+dlen=NNN` можно установить
+произвольный размер.
 
 В папке `source` находятся исходники RTL и программы. Верхний модуль - `testbench` с
 единственным входным сигналом `clock`. Генерация клока во внешнем модуле сделана для
@@ -25,7 +27,7 @@
 - QuestaSim 64 2021.1 (Revision: 2021.1)
 - Vivado 2021.1
 
-Время выполнения бенчмарка:
+Время выполнения бенчмарка на блоке 1кБ (мс):
 ```
     Icarus Verilog: TBD
     ModelSim: TBD

source/firmware/fw.mem

@@ -4,25 +4,26 @@ ffc10113
 0140006f
 10056513
 010007b7
-00a7aa23
+00a7ae23
 00008067
 fe010113
+00812c23
+01000437
+00442503
+00842583
 00010613
-000105b7
-00010537
 00112e23
-40d000ef
+409000ef
-00012703
+00012783
-010007b7
+00f42623
-00e7a223
+00412783
-00412703
+00f42823
-00e7a423
+00812783
-00812703
+00f42a23
-00e7a623
+00c12783
-00c12703
+00f42c23
-00e7a823
+00100793
-00100713
+00f42023
-00e7a023
 0000006f
 fe010113
 00912a23
@@ -242,7 +243,7 @@ ff877713
 06d76e63
 00001737
 00269693
-fb070713
+fb470713
 00e68733
 00072703
 00070067
@@ -288,7 +289,7 @@ f49ff06f
 0a088463
 fcd51ae3
 00001b37
-034b0793
+038b0793
 00471713
 16084a63
 01c10693
@@ -329,7 +330,7 @@ ce0402e3
 dadff06f
 0ad51463
 00001b37
-034b0793
+038b0793
 00471713
 01c10693
 00e787b3
@@ -474,7 +475,7 @@ ffffffb7
 00001e37
 00001637
 ffffcf13
-15000313
+15400313
 01010e93
 81060613
 800e0e13
@@ -551,7 +552,7 @@ fe010113
 01212a23
 00052903
 000018b7
-05488893
+05888893
 01312823
 01412623
 01512423
@@ -710,7 +711,7 @@ fb010113
 40c78933
 000015b7
 00090613
-25458593
+25858593
 00040513
 ec9ff0ef
 00042703
@@ -1002,39 +1003,39 @@ ffd78513
 00008067
 ffc78513
 00008067
-000005f8
+000005fc
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-000005e0
+000005e4
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-000005d4
+000005d8
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-00000440
+00000444
-000005ec
+000005f0
 33323130
 37363534
 42413938
@@ -16381,4 +16382,3 @@ eb86d391
 00000000
 00000000
 00000000
-00000000

source/firmware/main.c

@@ -4,9 +4,6 @@
 
 #include <stdint.h>
 
-#define DATA_ADDR 0x10000
-#define DATA_LEN  0x10000
-
 void put_char(char c)
 {
     IO_REG_CONSOLE = c | IO_REG_CONSOLE_SEND;
@@ -15,8 +12,13 @@ void put_char(char c)
 int main(void)
 {
     uint8_t result[16];
+    uint8_t *daddr;
+    uint32_t dlen;
 
-    md5Buf((uint8_t *)DATA_ADDR, DATA_LEN, result);
+    daddr = (uint8_t *)IO_REG_DATA_ADDR;
+    dlen  = IO_REG_DATA_LEN;
+
+    md5Buf(daddr, dlen, result);
 
     IO_REG_MD5_OUT0 = *(uint32_t *)(result + 0);
     IO_REG_MD5_OUT1 = *(uint32_t *)(result + 4);

source/io.reg

@@ -9,6 +9,14 @@
       (info "Control register")
       (bits 1 "stop" w (reset #b0)))
 
+ (reg "data_addr"
+      (info "Data block address")
+      (bits 32 "addr" r))
+
+ (reg "data_len"
+      (info "Data block length")
+      (bits 32 "len" r))
+
  (reg "md5_out0"
       (info "Bytes 0..3 of MD5 sum")
       (bits 32 "data" w))

source/io_reg.h

@@ -7,28 +7,38 @@
 #define IO_REG_CTRL (*(volatile uint32_t*)(IO_REG_BASE + 0x00000000))
 #define IO_REG_CTRL_STOP (1 << 0)
 
+/* -- Register 'DATA_ADDR' -- */
+#define IO_REG_DATA_ADDR (*(volatile uint32_t*)(IO_REG_BASE + 0x00000004))
+#define IO_REG_DATA_ADDR_ADDR__MASK 0xffffffff
+#define IO_REG_DATA_ADDR_ADDR__SHIFT 0
+
+/* -- Register 'DATA_LEN' -- */
+#define IO_REG_DATA_LEN (*(volatile uint32_t*)(IO_REG_BASE + 0x00000008))
+#define IO_REG_DATA_LEN_LEN__MASK 0xffffffff
+#define IO_REG_DATA_LEN_LEN__SHIFT 0
+
 /* -- Register 'MD5_OUT0' -- */
-#define IO_REG_MD5_OUT0 (*(volatile uint32_t*)(IO_REG_BASE + 0x00000004))
+#define IO_REG_MD5_OUT0 (*(volatile uint32_t*)(IO_REG_BASE + 0x0000000c))
 #define IO_REG_MD5_OUT0_DATA__MASK 0xffffffff
 #define IO_REG_MD5_OUT0_DATA__SHIFT 0
 
 /* -- Register 'MD5_OUT1' -- */
-#define IO_REG_MD5_OUT1 (*(volatile uint32_t*)(IO_REG_BASE + 0x00000008))
+#define IO_REG_MD5_OUT1 (*(volatile uint32_t*)(IO_REG_BASE + 0x00000010))
 #define IO_REG_MD5_OUT1_DATA__MASK 0xffffffff
 #define IO_REG_MD5_OUT1_DATA__SHIFT 0
 
 /* -- Register 'MD5_OUT2' -- */
-#define IO_REG_MD5_OUT2 (*(volatile uint32_t*)(IO_REG_BASE + 0x0000000c))
+#define IO_REG_MD5_OUT2 (*(volatile uint32_t*)(IO_REG_BASE + 0x00000014))
 #define IO_REG_MD5_OUT2_DATA__MASK 0xffffffff
 #define IO_REG_MD5_OUT2_DATA__SHIFT 0
 
 /* -- Register 'MD5_OUT3' -- */
-#define IO_REG_MD5_OUT3 (*(volatile uint32_t*)(IO_REG_BASE + 0x00000010))
+#define IO_REG_MD5_OUT3 (*(volatile uint32_t*)(IO_REG_BASE + 0x00000018))
 #define IO_REG_MD5_OUT3_DATA__MASK 0xffffffff
 #define IO_REG_MD5_OUT3_DATA__SHIFT 0
 
 /* -- Register 'CONSOLE' -- */
-#define IO_REG_CONSOLE (*(volatile uint32_t*)(IO_REG_BASE + 0x00000014))
+#define IO_REG_CONSOLE (*(volatile uint32_t*)(IO_REG_BASE + 0x0000001c))
 #define IO_REG_CONSOLE_DATA__MASK 0x000000ff
 #define IO_REG_CONSOLE_DATA__SHIFT 0
 #define IO_REG_CONSOLE_SEND (1 << 8)

source/io_reg.txt

@@ -1,14 +1,16 @@
 Register map of IO_REG (base: 0x1000000)
 ========================================
 
-  |   Offset   |   Name   |       Description       |
+  |   Offset   |   Name    |       Description       |
-  |------------+----------+-------------------------|
+  |------------+-----------+-------------------------|
-  | 0x00000000 | CTRL     | Control register        |
+  | 0x00000000 | CTRL      | Control register        |
-  | 0x00000004 | MD5_OUT0 | Bytes 0..3 of MD5 sum   |
+  | 0x00000004 | DATA_ADDR | Data block address      |
-  | 0x00000008 | MD5_OUT1 | Bytes 4..7 of MD5 sum   |
+  | 0x00000008 | DATA_LEN  | Data block length       |
-  | 0x0000000c | MD5_OUT2 | Bytes 8..11 of MD5 sum  |
+  | 0x0000000c | MD5_OUT0  | Bytes 0..3 of MD5 sum   |
-  | 0x00000010 | MD5_OUT3 | Bytes 12..15 of MD5 sum |
+  | 0x00000010 | MD5_OUT1  | Bytes 4..7 of MD5 sum   |
-  | 0x00000014 | CONSOLE  | Virtual console port    |
+  | 0x00000014 | MD5_OUT2  | Bytes 8..11 of MD5 sum  |
+  | 0x00000018 | MD5_OUT3  | Bytes 12..15 of MD5 sum |
+  | 0x0000001c | CONSOLE   | Virtual console port    |
 
 
 CTRL Register (0x00000000)
@@ -21,7 +23,27 @@ CTRL Register (0x00000000)
   |    0 | STOP | WO   | 0     |             |
 
 
-MD5_OUT0 Register (0x00000004)
+DATA_ADDR Register (0x00000004)
+-------------------------------
+
+  Data block address
+
+  | Bits | Name | Mode | Reset | Description |
+  |------+------+------+-------+-------------|
+  | 31:0 | ADDR | RO   | 0     |             |
+
+
+DATA_LEN Register (0x00000008)
+------------------------------
+
+  Data block length
+
+  | Bits | Name | Mode | Reset | Description |
+  |------+------+------+-------+-------------|
+  | 31:0 | LEN  | RO   | 0     |             |
+
+
+MD5_OUT0 Register (0x0000000c)
 ------------------------------
 
   Bytes 0..3 of MD5 sum
@@ -31,7 +53,7 @@ MD5_OUT0 Register (0x00000004)
   | 31:0 | DATA | WO   | 0     |             |
 
 
-MD5_OUT1 Register (0x00000008)
+MD5_OUT1 Register (0x00000010)
 ------------------------------
 
   Bytes 4..7 of MD5 sum
@@ -41,7 +63,7 @@ MD5_OUT1 Register (0x00000008)
   | 31:0 | DATA | WO   | 0     |             |
 
 
-MD5_OUT2 Register (0x0000000c)
+MD5_OUT2 Register (0x00000014)
 ------------------------------
 
   Bytes 8..11 of MD5 sum
@@ -51,7 +73,7 @@ MD5_OUT2 Register (0x0000000c)
   | 31:0 | DATA | WO   | 0     |             |
 
 
-MD5_OUT3 Register (0x00000010)
+MD5_OUT3 Register (0x00000018)
 ------------------------------
 
   Bytes 12..15 of MD5 sum
@@ -61,7 +83,7 @@ MD5_OUT3 Register (0x00000010)
   | 31:0 | DATA | WO   | 0     |             |
 
 
-CONSOLE Register (0x00000014)
+CONSOLE Register (0x0000001c)
 -----------------------------
 
   Virtual console port

source/io_reg.v

@@ -17,6 +17,12 @@ module io_reg
    /* ---- 'ctrl' ---- */
    output wire o_ctrl_stop,
 
+   /* ---- 'data_addr' ---- */
+   input wire [31:0] i_data_addr_addr,
+
+   /* ---- 'data_len' ---- */
+   input wire [31:0] i_data_len_len,
+
    /* ---- 'md5_out0' ---- */
    output wire [31:0] o_md5_out0_data,
 
@@ -40,6 +46,8 @@ module io_reg
 
   /* ---- Address decoder ---- */
   wire ctrl_select;
+  wire data_addr_select;
+  wire data_len_select;
   wire md5_out0_select;
   wire md5_out1_select;
   wire md5_out2_select;
@@ -51,27 +59,39 @@ module io_reg
     i_addr[3] == 1'b0 &&
     i_addr[4] == 1'b0;
 
-  assign md5_out0_select =
+  assign data_addr_select =
     i_addr[2] == 1'b1 &&
     i_addr[3] == 1'b0 &&
     i_addr[4] == 1'b0;
 
-  assign md5_out1_select =
+  assign data_len_select =
     i_addr[2] == 1'b0 &&
     i_addr[3] == 1'b1 &&
     i_addr[4] == 1'b0;
 
-  assign md5_out2_select =
+  assign md5_out0_select =
     i_addr[2] == 1'b1 &&
     i_addr[3] == 1'b1 &&
     i_addr[4] == 1'b0;
 
+  assign md5_out1_select =
+    i_addr[2] == 1'b0 &&
+    i_addr[3] == 1'b0 &&
+    i_addr[4] == 1'b1;
+
+  assign md5_out2_select =
+    i_addr[2] == 1'b1 &&
+    i_addr[3] == 1'b0 &&
+    i_addr[4] == 1'b1;
+
   assign md5_out3_select =
     i_addr[2] == 1'b0 &&
+    i_addr[3] == 1'b1 &&
     i_addr[4] == 1'b1;
 
   assign console_select =
     i_addr[2] == 1'b1 &&
+    i_addr[3] == 1'b1 &&
     i_addr[4] == 1'b1;
 
 
@@ -179,6 +199,8 @@ module io_reg
 
   /* ---- Read multiplexer ---- */
   reg [31:0] data_ctrl;
+  reg [31:0] data_data_addr;
+  reg [31:0] data_data_len;
   reg [31:0] data_md5_out0;
   reg [31:0] data_md5_out1;
   reg [31:0] data_md5_out2;
@@ -187,6 +209,8 @@ module io_reg
 
   assign o_data = 
     data_ctrl |
+    data_data_addr |
+    data_data_len |
     data_md5_out0 |
     data_md5_out1 |
     data_md5_out2 |
@@ -195,12 +219,22 @@ module io_reg
 
   always @(*) begin
     data_ctrl = 32'd0;
+    data_data_addr = 32'd0;
+    data_data_len = 32'd0;
     data_md5_out0 = 32'd0;
     data_md5_out1 = 32'd0;
     data_md5_out2 = 32'd0;
     data_md5_out3 = 32'd0;
     data_console = 32'd0;
 
+    if (data_addr_select) begin
+      data_data_addr[31:0] = i_data_addr_addr;
+    end
+
+    if (data_len_select) begin
+      data_data_len[31:0] = i_data_len_len;
+    end
+
     if (console_select) begin
       data_console[7:0] = i_console_data;
       data_console[8] = i_console_send;

source/md5calculator.sv

@@ -4,7 +4,8 @@ module md5calculator
   (input clock,
    input reset,
    output done,
-   // input [31:0] data_in,
+   input [31:0] md5_data_addr,
+   input [31:0] md5_data_len,
    output [127:0] md5);
 
     parameter MEM_ADDR_WIDTH = 16;
@@ -193,7 +194,8 @@ module md5calculator
        .o_ctrl_stop(ctrl_stop),
 
        // MD5
-       // .i_md5_data_data(data_in),
+       .i_data_addr_addr(md5_data_addr),
+       .i_data_len_len(md5_data_len),
        .o_md5_out0_data(md5_out0),
        .o_md5_out1_data(md5_out1),
        .o_md5_out2_data(md5_out2),

source/testbench.sv

@@ -1,9 +1,11 @@
 `timescale 1ps/1ps
 
-
 module testbench (input clock);
     localparam CPU_COUNT = 1024;
+    localparam DATA_ADDR = 32'h00010000;
+    localparam DATA_LEN = 1024;
 
+    logic [31:0] data_len;
     logic [CPU_COUNT-1:0] done_all;
 
     for (genvar ncpu = 0; ncpu < CPU_COUNT; ncpu = ncpu + 1) begin : cpus
@@ -15,12 +17,20 @@ module testbench (input clock);
 
         assign done_all[ncpu] = done;
 
-        md5calculator cpu(.clock, .reset, .done, .md5);
+        md5calculator cpu
+          (.clock, .reset, .done,
+           .md5_data_addr(DATA_ADDR),
+           .md5_data_len(data_len),
+           .md5(md5));
 
         initial
           for (int n = 0; n < (2 ** (cpu.rom.ADDR_WIDTH-2)); n += 1)
             cpu.rom.ram[n] = ncpu;
 
+        initial
+          if(!$value$plusargs("dlen=%d", data_len))
+            data_len = DATA_LEN;
+
         initial begin
             reset = 1'b1;
             repeat($urandom % 5 + 2) @(posedge clock);
@@ -36,7 +46,6 @@ module testbench (input clock);
     initial begin
         $display("--- BENCH BEGIN ---");
 
-
         repeat(5) @(posedge clock);
         while ((&done_all) == 1'b0) @(posedge clock);
         @(posedge clock);

test-iverilog/__run.sh

@@ -1,3 +1,9 @@
 #!/usr/bin/env bash
 
-vvp -n ./top
+if [ -n "$1" ]; then
+    dlen_arg="+dlen=$1"
+else
+    dlen_arg=""
+fi
+
+vvp -n ./top $dlen_arg

test-modelsim/__run.sh

@@ -1,3 +1,9 @@
 #!/usr/bin/env bash
 
-vsim -batch -voptargs=+acc=npr -do "run -all" -quiet -lib testbench top
+if [ -n "$1" ]; then
+    dlen_arg="+dlen=$1"
+else
+    dlen_arg=""
+fi
+
+vsim -batch -voptargs=+acc=npr -do "run -all" -quiet $dlen_arg -lib testbench top

test-verilator/__run.sh

@@ -1,3 +1,9 @@
 #!/usr/bin/env bash
 
-./testbench/testbench
+if [ -n "$1" ]; then
+    dlen_arg="+dlen=$1"
+else
+    dlen_arg=""
+fi
+
+./testbench/testbench $dlen_arg

test-xcelium/__run.sh

@@ -1,3 +1,9 @@
 #!/usr/bin/env bash
 
-xmsim -status top
+if [ -n "$1" ]; then
+    dlen_arg="+dlen=$1"
+else
+    dlen_arg=""
+fi
+
+xmsim -status top $dlen_arg

test-xsim/.gitignore

@@ -1,4 +1,4 @@
 webtalk*
-xsim.*
+xsim*
 xelab.*
 xvlog.*

test-xsim/__run.sh

@@ -1,4 +1,9 @@
 #!/usr/bin/env bash
 
-#vsim -c -batch -voptargs=+acc=npr -do "run -all" -quiet -lib testbench top
+if [ -n "$1" ]; then
-xsim top --runall
+    dlen_arg="-testplusarg dlen=$1"
+else
+    dlen_arg=""
+fi
+
+xsim top $dlen_arg --runall