21 lines
634 B
Diff
21 lines
634 B
Diff
--- simbench-all.v 2025-01-08 22:09:06.737402979 +0300
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+++ simbench-all.v1 2025-01-08 22:08:27.142909974 +0300
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@@ -1,3 +1,4 @@
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+`timescale 1ps/1ps
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module top;
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parameter CPU_COUNT = 1024;
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reg clock = 1'b0;
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@@ -13,10 +14,9 @@
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wire [CPU_COUNT - 1:0] done_all;
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reg signed [31:0] cycle = 0;
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always @(posedge clock) cycle <= cycle + 1;
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- genvar _gv_ncpu_1;
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+ genvar ncpu;
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generate
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- for (_gv_ncpu_1 = 0; _gv_ncpu_1 < CPU_COUNT; _gv_ncpu_1 = _gv_ncpu_1 + 1) begin : cpus
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- localparam ncpu = _gv_ncpu_1;
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+ for (ncpu = 0; ncpu < CPU_COUNT; ncpu = ncpu + 1) begin : cpus
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wire done;
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reg done_ack = 1'b0;
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wire reset;
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