99 lines
2.1 KiB
Verilog
99 lines
2.1 KiB
Verilog
// This file is auto-generated. Do not edit
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module io_reg
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(input wire clock,
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input wire reset,
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/* ---- Access bus ---- */
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/* verilator lint_off UNUSED */
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input wire [31:0] i_addr,
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input wire [31:0] i_data,
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output wire [31:0] o_data,
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input wire [3:0] i_ben,
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input wire i_write,
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input wire i_read,
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/* verilator lint_on UNUSED */
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/* ---- 'ctrl' ---- */
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output wire o_ctrl_stop,
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/* ---- 'console' ---- */
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output wire o_console__rnotify,
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input wire [7:0] i_console_data,
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output wire [7:0] o_console_data,
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output wire o_console_send_hsreq,
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input wire i_console_send_hsack,
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input wire i_console_send,
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input wire i_console_valid);
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/* ---- Address decoder ---- */
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wire ctrl_select;
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wire console_select;
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assign ctrl_select =
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i_addr[2] == 1'b0;
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assign console_select =
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i_addr[2] == 1'b1;
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/* ---- 'ctrl' ---- */
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reg ctrl_stop;
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assign o_ctrl_stop = ctrl_stop;
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always @(posedge clock)
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if (reset)
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ctrl_stop <= 1'b0;
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else
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if (ctrl_select && i_write) begin
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if (i_ben[0]) ctrl_stop <= i_data[0];
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end
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/* ---- 'console' ---- */
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reg [7:0] console_data;
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assign o_console_data = console_data;
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always @(posedge clock)
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if (reset)
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console_data <= 8'b0;
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else
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if (console_select && i_write) begin
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if (i_ben[0]) console_data[7:0] <= i_data[7:0];
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end
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reg console_send_hsreq;
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assign o_console_send_hsreq = console_send_hsreq;
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always @(posedge clock)
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if (reset)
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console_send_hsreq <= 1'b0;
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else begin
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if (console_select && i_write && i_ben[1]) console_send_hsreq <= i_data[8];
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else console_send_hsreq <= console_send_hsreq & (~i_console_send_hsack);
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end
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assign o_console__rnotify = console_select & i_read;
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/* ---- Read multiplexer ---- */
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reg [31:0] data_ctrl;
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reg [31:0] data_console;
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assign o_data =
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data_ctrl |
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data_console;
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always @(*) begin
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data_ctrl = 32'd0;
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data_console = 32'd0;
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if (console_select) begin
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data_console[7:0] = i_console_data;
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data_console[8] = i_console_send;
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data_console[9] = i_console_valid;
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end
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end
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endmodule // io_reg
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