108 lines
2.2 KiB
C++
108 lines
2.2 KiB
C++
#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <libgen.h>
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#include <verilated_vcd_c.h>
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#include "Vtestbench_top.h"
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#define DUMPFILE "testbench_top.vcd"
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#define PIPE_FILE "lcd_pipe"
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/* Clock period in timescale units
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* In datapath.sv uses 100ps time unit */
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#define CLOCK_PERIOD 2
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#define TIMESCALE 20000
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/* Simulation time */
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uint64_t simtime = 0;
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/* Clock cycle counter */
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uint64_t cycle = 0;
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/* Called by $time in Verilog */
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double sc_time_stamp() {
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return simtime;
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}
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int main(int argc, char **argv)
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{
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Verilated::commandArgs(argc, argv);
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/* Create model instance */
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Vtestbench_top *dp = new Vtestbench_top;
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/* Enable trace if compiled with --trace flag */
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#if (VM_TRACE == 1)
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VerilatedVcdC *vcd = NULL;
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const char* trace_flag = Verilated::commandArgsPlusMatch("trace");
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if (trace_flag && (strcmp(trace_flag, "+trace") == 0))
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{
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Verilated::traceEverOn(true);
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vcd = new VerilatedVcdC;
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dp->trace(vcd, 99);
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vcd->open(DUMPFILE);
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}
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#endif
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/* Open pipe */
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FILE *o_file = fopen(PIPE_FILE, "w");
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if (!o_file) {
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printf("ERROR: Can't open file/pipe '%s'\n", PIPE_FILE);
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delete dp;
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return -1;
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}
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int posedge_clock = 0;
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int data_loops = 6;
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uint64_t check_cycle;
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/* Initial */
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dp->reset = 1;
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dp->clock = 0;
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while (!Verilated::gotFinish())
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{
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posedge_clock = 0;
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if ((simtime % (CLOCK_PERIOD/2)) == 0) {
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dp->clock = !dp->clock;
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if (dp->clock) {
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posedge_clock = 1;
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cycle ++;
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}
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}
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/* release reset at 200 simulation cycle */
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if (simtime == 200) dp->reset = 0;
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dp->eval();
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/* ouput data */
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if (posedge_clock && !dp->reset && dp->strobe)
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fprintf(o_file, "%i %i %i %i %i\n",
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dp->x, dp->y, dp->r << 2, dp->g << 2, dp->b << 2);
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#if (VM_TRACE == 1)
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if (vcd)
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vcd->dump(simtime * TIMESCALE);
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#endif
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simtime ++;
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}
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dp->final();
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printf("[%lu] Stop simulation\n", simtime);
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#if (VM_TRACE == 1)
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if (vcd) vcd->close();
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#endif
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fclose(o_file);
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delete dp;
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return 0;
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}
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