50 lines
923 B
Systemverilog
50 lines
923 B
Systemverilog
`timescale 1ns/100ps
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module tb_hsl2rgb;
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logic clock = 1'b0;
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logic reset = 1'b1;
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/* Master clock 100MHz (10ns period) */
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always #(10ns/2) clock <= ~clock;
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logic [7:0] h, s, l;
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logic [7:0] r, g, b;
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logic valid, ready;
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hsl2rgb DUT
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(.clock, .reset,
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.h, .s, .l,
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.ready_i(ready),
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.r, .g, .b,
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.valid_o(valid));
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always_ff @ (posedge clock)
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if (valid)
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$display("%d %d %d", r, g, b);
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initial begin
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reset = 1'b1;
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ready = 1'b0;
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repeat(10) @(posedge clock) #1;
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reset = 1'b0;
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@(posedge clock) #1;
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h = 8'd128;
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s = 8'd255;
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l = 8'd130;
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ready = 1'b1;
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@(posedge clock) #1;
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ready = 1'b0;
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repeat(20) @(posedge clock);
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$finish;
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end
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initial begin
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$dumpfile("tb_hsl2rgb.vcd");
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$dumpvars;
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end
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endmodule // tb_hsl2rgb
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