83 lines
1.7 KiB
Systemverilog
83 lines
1.7 KiB
Systemverilog
`timescale 1ns/100ps
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`default_nettype none
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module circle_1024
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(input wire clock,
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input wire reset,
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input wire [9:0] angle,
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input wire [7:0] r,
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input wire [7:0] x0,
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input wire [7:0] y0,
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output wire [7:0] x,
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output wire [7:0] y,
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input wire req_i,
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output reg ack_o);
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localparam QUADR_LEN = 256;
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localparam QUADR_ROM_FILE = "quadrant_256.rom";
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localparam QUADR_CW = $clog2(QUADR_LEN);
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logic [15:0] q_rom[QUADR_LEN];
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initial $readmemh(QUADR_ROM_FILE, q_rom, 0, QUADR_LEN-1);
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logic [QUADR_CW-1:0] q_addr;
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logic [7:0] kx, ky;
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always_ff @ (posedge clock)
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{kx, ky} <= q_rom[q_addr];
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logic [15:0] macx_o, macy_o;
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logic xsub, ysub;
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ice40_2mac8x8 circle_mac
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(.clock, .reset,
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.a0(r),
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.b0(kx),
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.s0({x0, 8'b0}),
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.sub0(xsub),
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.y0(macx_o),
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.a1(r),
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.b1(ky),
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.s1({y0, 8'b0}),
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.sub1(ysub),
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.y1(macy_o));
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assign q_addr = angle[8] ? 8'd255 - angle[7:0] : angle[7:0];
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assign xsub = angle[9];
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assign ysub = angle[8] == angle[9] ? 1'b0 : 1'b1;
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assign x = macx_o[15:8];
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assign y = macy_o[15:8];
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enum int unsigned {
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ST_IDLE = 0,
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ST_GET_K,
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ST_MAC
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} state;
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always_ff @(posedge clock, posedge reset)
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if (reset) begin
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state <= ST_IDLE;
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ack_o <= 1'b0;
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end
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else
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case (state)
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ST_IDLE:
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if (req_i)
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state <= ST_GET_K;
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ST_GET_K: begin
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ack_o <= 1'b1;
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state <= ST_MAC;
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end
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ST_MAC: begin
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ack_o <= 1'b0;
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state <= ST_IDLE;
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end
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endcase
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endmodule // circle
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