82 lines
2.4 KiB
Systemverilog
82 lines
2.4 KiB
Systemverilog
`timescale 1ns/100ps
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`default_nettype none
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/* verilator lint_off PINCONNECTEMPTY */
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module ice40_2mac8x8 #(parameter SIGNED = 0)
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(input wire clock,
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input wire reset,
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input wire [7:0] a0,
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input wire [7:0] b0,
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input wire [15:0] s0,
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input wire sub0,
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output wire [15:0] y0,
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input wire [7:0] a1,
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input wire [7:0] b1,
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input wire [15:0] s1,
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input wire sub1,
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output wire [15:0] y1);
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/* register 'sub' input */
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logic sub0_r, sub1_r;
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always_ff @ (posedge clock) begin
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sub0_r <= sub0;
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sub1_r <= sub1;
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end
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logic [31:0] mac_o;
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assign {y0, y1} = mac_o;
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SB_MAC16
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#(.NEG_TRIGGER(1'b0),
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.C_REG(1'b1), // Registered C
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.A_REG(1'b1), // Registered A
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.B_REG(1'b1), // Registered B
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.D_REG(1'b1), // Registered D
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.TOP_8x8_MULT_REG(1'b0),
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.BOT_8x8_MULT_REG(1'b0),
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.PIPELINE_16x16_MULT_REG1(1'b0),
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.PIPELINE_16x16_MULT_REG2(1'b0),
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.TOPOUTPUT_SELECT(2'b00), // TOP output - ADD/SUB unregistered
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.TOPADDSUB_LOWERINPUT(2'b01), // TOP adder input 1 - 8x8 top multiplier output
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.TOPADDSUB_UPPERINPUT(1'b1), // TOP adder input 2 - input C
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.TOPADDSUB_CARRYSELECT(2'b00), // TOP adder carry input - constant 0
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.BOTOUTPUT_SELECT(2'b00), // BOT output - ADD/SUB unregistered
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.BOTADDSUB_LOWERINPUT(2'b01), // BOT adder input 1 - 8x8 bot multiplier output
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.BOTADDSUB_UPPERINPUT(1'b1), // BOT adder input 2 - input D
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.BOTADDSUB_CARRYSELECT(2'b00), // BOT adder carry input - constant 0
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.MODE_8x8(1'b1),
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.A_SIGNED(SIGNED),
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.B_SIGNED(SIGNED))
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mac_r
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(.CLK(clock),
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.CE(1'b1),
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.C(s0),
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.A({a0, a1}),
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.B({b0, b1}),
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.D(s1),
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.AHOLD(1'b0),
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.BHOLD(1'b0),
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.CHOLD(1'b0),
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.DHOLD(1'b0),
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.IRSTTOP(reset),
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.IRSTBOT(reset),
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.ORSTTOP(reset),
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.ORSTBOT(reset),
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.OLOADTOP(1'b0),
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.OLOADBOT(1'b0),
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.ADDSUBTOP(sub0_r),
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.ADDSUBBOT(sub1_r),
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.OHOLDTOP(1'b0),
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.OHOLDBOT(1'b0),
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.CI(1'b0),
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.ACCUMCI(1'b0),
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.SIGNEXTIN(1'b0),
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.O(mac_o),
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.CO(),
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.ACCUMCO(),
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.SIGNEXTOUT());
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endmodule // ice40_macadd16x16
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