157 lines
4.0 KiB
Systemverilog
157 lines
4.0 KiB
Systemverilog
`timescale 1ns/100ps
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`default_nettype none
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module lcd_ili9341_4spi
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(input wire clock,
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input wire reset,
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input wire csn_i,
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input wire clk_i,
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input wire sdi_i,
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input wire dcn_i,
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output int x_o,
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output int y_o,
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output logic [7:0] r_o,
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output logic [7:0] g_o,
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output logic [7:0] b_o,
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output logic strobe_o);
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logic [7:0] readed;
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logic [7:0] spi_sr;
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int bit_cntr;
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logic clk_prev;
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logic rstrobe;
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always_ff @ (posedge clock) clk_prev <= clk_i;
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always_ff @(posedge clock, posedge csn_i)
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if (csn_i || reset) begin
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bit_cntr <= 0;
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end
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else begin
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if (clk_prev == 1'b0 &&
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clk_i == 1'b1)
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begin
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spi_sr <= { spi_sr[6:0], sdi_i };
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bit_cntr <= bit_cntr + 1;
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end
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if (bit_cntr == 8) begin
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readed <= spi_sr;
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rstrobe <= 1'b1;
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bit_cntr <= 0;
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end
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else
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rstrobe <= 1'b0;
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end
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enum int unsigned {
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ST_IDLE = 0,
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ST_CADDR,
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ST_PADDR,
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ST_MEM_WRITE
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} state;
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logic [15:0] x_beg;
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logic [15:0] x_end;
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logic [15:0] y_beg;
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logic [15:0] y_end;
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initial begin
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x_beg = 0;
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x_end = 239;
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y_beg = 0;
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y_end = 319;
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end
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int n;
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int x, y;
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logic [7:0] tmp;
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always_ff @ (posedge clock, posedge csn_i)
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if (csn_i || reset) begin
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state <= ST_IDLE;
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n <= 0;
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strobe_o <= 1'b0;
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end
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else begin
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strobe_o <= 1'b0;
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if (rstrobe) begin
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if (~dcn_i) begin
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case (readed)
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8'h2a: state <= ST_CADDR;
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8'h2b: state <= ST_PADDR;
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8'h2c: begin
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x <= int'(x_beg);
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y <= int'(y_beg);
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state <= ST_MEM_WRITE;
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end
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default: begin end
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endcase
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n <= 0;
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end
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else
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case (state)
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ST_CADDR: begin
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n <= n + 1;
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case (n)
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0: x_beg[15:8] <= readed;
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1: x_beg[7:0] <= readed;
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2: x_end[15:8] <= readed;
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3: x_end[7:0] <= readed;
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endcase
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end
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ST_PADDR: begin
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n <= n + 1;
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case (n)
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0: y_beg[15:8] <= readed;
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1: y_beg[7:0] <= readed;
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2: y_end[15:8] <= readed;
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3: y_end[7:0] <= readed;
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endcase
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end
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ST_MEM_WRITE: begin
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if (n == 0) begin
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n <= 1;
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tmp <= readed;
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end
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else begin
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n <= 0;
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// $display("%d %d %d %d %d", x, y,
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// { tmp[7:3], 1'b0 },
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// { tmp[2:0], readed[7:5] },
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// { readed[4:0], 1'b0 });
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x_o <= x;
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y_o <= y;
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r_o <= { 2'b00, tmp[7:3], 1'b0 };
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g_o <= { 2'b00, tmp[2:0], readed[7:5] };
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b_o <= { 2'b00, readed[4:0], 1'b0 };
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strobe_o <= 1'b1;
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x <= x + 1;
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if (x == int'(x_end)) begin
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x <= int'(x_beg);
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y <= y + 1;
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if (y == int'(y_end))
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y <= int'(y_beg);
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end
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end
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end
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endcase
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end
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end
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endmodule // lcd_ili9341_4spi
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