42 lines
720 B
Systemverilog
42 lines
720 B
Systemverilog
`timescale 1ns/100ps
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`default_nettype none
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/* verilator lint_off PINMISSING */
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module testbench_top
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(input wire clock,
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input wire reset,
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output int x,
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output int y,
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output [7:0] r,
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output [7:0] g,
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output [7:0] b,
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output strobe);
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logic csn, mosi, clk, dcn;
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sugar_lissajous DUT
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(.CLK12(clock),
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.P1_3(1'b0),
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.P1_10(1'b1),
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.P2_3(dcn),
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.P2_9(clk),
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.P2_11(mosi),
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.P2_12(csn));
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lcd_ili9341_4spi LCD
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(.clock, .reset,
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.csn_i(csn),
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.clk_i(clk),
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.sdi_i(mosi),
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.dcn_i(dcn),
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.x_o(x),
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.y_o(y),
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.r_o(r),
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.g_o(g),
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.b_o(b),
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.strobe_o(strobe));
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endmodule // testbench_top
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