71 lines
1.3 KiB
Systemverilog
71 lines
1.3 KiB
Systemverilog
`timescale 1ns/100ps
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module tb_fig_drawer;
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logic clock = 1'b0;
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logic reset = 1'b1;
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/* Master clock 100MHz (10ns period) */
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always #(10ns/2) clock <= ~clock;
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logic [7:0] x;
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logic [8:0] y;
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logic [7:0] h, s, v;
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logic req, ack;
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logic [7:0] fb_x;
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logic [8:0] fb_y;
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logic [15:0] fb_color;
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logic fb_req, fb_ack;
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fig_drawer DUT
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(.clock, .reset,
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.x_i(x), .y_i(y),
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.h_i(h), .s_i(s), .v_i(v),
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.req_i(req), .ack_o(ack),
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.fb_x_o(fb_x),
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.fb_y_o(fb_y),
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.fb_color_o(fb_color),
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.fb_req_o(fb_req),
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.fb_ack_i(fb_ack));
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int fb_lat_n;
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always_ff @ (posedge clock) begin
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fb_ack <= 1'b0;
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if (fb_req)
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if (fb_lat_n == 2) begin
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fb_ack <= 1'b1;
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fb_lat_n <= 0;
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end
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else fb_lat_n <= fb_lat_n + 1;
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end
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always_ff @ (posedge clock)
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if (ack)
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req <= 1'b0;
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initial begin
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reset <= 1'b1;
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repeat(10) @(posedge clock);
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reset <= 1'b0;
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@(posedge clock);
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x <= 'd20;
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y <= 'd50;
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h <= 50;
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s <= 100;
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v <= 150;
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req <= 1'b1;
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repeat(1000) @(posedge clock);
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$finish;
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end
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initial begin
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$dumpfile("tb_fig_drawer.vcd");
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$dumpvars;
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end
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endmodule // tb_fig_drawer
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