70 lines
1.8 KiB
Systemverilog
70 lines
1.8 KiB
Systemverilog
`timescale 1ns/100ps
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module tb_fig_ring;
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logic clock = 1'b0;
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logic reset = 1'b1;
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/* Master clock 100MHz (10ns period) */
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always #(10ns/2) clock <= ~clock;
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logic pt_ack_o;
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logic [7:0] fig_x_o;
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logic [8:0] fig_y_o;
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logic [7:0] fig_h_o;
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logic [7:0] fig_s_o;
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logic [7:0] fig_v_o;
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logic fig_req_o;
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logic [7:0] pt_x;
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logic [7:0] pt_y;
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logic [7:0] pt_h;
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logic pt_req_i;
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logic fig_ack_i;
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fig_ring DUT (/*AUTOINST*/
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// Outputs
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.pt_ack_o (pt_ack_o),
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.fig_x_o (fig_x_o[7:0]),
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.fig_y_o (fig_y_o[8:0]),
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.fig_h_o (fig_h_o[7:0]),
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.fig_s_o (fig_s_o[7:0]),
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.fig_v_o (fig_v_o[7:0]),
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.fig_req_o (fig_req_o),
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// Inputs
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.clock (clock),
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.reset (reset),
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.pt_x (pt_x[7:0]),
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.pt_y (pt_y[7:0]),
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.pt_h (pt_h[7:0]),
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.pt_req_i (pt_req_i),
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.fig_ack_i (fig_ack_i));
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assign fig_ack_i = 1'b1;
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always_ff @ (posedge clock)
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if (pt_ack_o)
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pt_req_i <= 1'b0;
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initial begin
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reset = 1'b1;
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pt_req_i = 1'b0;
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repeat(10) @(posedge clock) #1;
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reset = 1'b0;
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@(posedge clock) #1;
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pt_x = 0;
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pt_y = 0;
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pt_h = 100;
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pt_req_i = 1'b1;
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repeat(1000) @(posedge clock) #1;
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$finish;
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end
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initial begin
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$dumpfile("tb_fig_ring.vcd");
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$dumpvars;
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end
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endmodule // tb_fig_ring
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