34 lines
713 B
Systemverilog
34 lines
713 B
Systemverilog
`timescale 1ns/100ps
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`default_nettype none
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`include "assert.vh"
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module tick_generator #(parameter PERIOD = 1000)
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(input wire clock,
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input wire reset,
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output reg tick_o);
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initial begin
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`assert(PERIOD > 1);
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end
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localparam TICK_CW = $clog2(PERIOD);
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logic [TICK_CW-1:0] cntr;
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always_ff @(posedge clock, posedge reset)
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if (reset) begin
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cntr <= '0;
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tick_o <= 1'b0;
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end
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else begin
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if (cntr == (PERIOD-1)) begin
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cntr <= '0;
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tick_o <= 1'b1;
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end
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else begin
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cntr <= cntr + 1'b1;
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tick_o <= 1'b0;
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end
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end
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endmodule // tick_generator
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