61 lines
1.0 KiB
Systemverilog
61 lines
1.0 KiB
Systemverilog
`timescale 1ns/100ps
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module tb_circle;
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logic clock = 1'b0;
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logic reset = 1'b1;
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/* Master clock 100MHz (10ns period) */
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always #(10ns/2) clock <= ~clock;
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logic [9:0] angle;
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logic [7:0] r;
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logic [7:0] x0;
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logic [7:0] y0;
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logic [7:0] x;
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logic [7:0] y;
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logic req, ack;
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circle_1024 DUT
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(.clock, .reset,
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.angle,
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.r,
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.x0,
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.y0,
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.x,
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.y,
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.req_i(req),
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.ack_o(ack));
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initial begin
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reset = 1'b1;
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req = 1'b0;
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repeat(10) @(posedge clock) #1;
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reset = 1'b0;
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@(posedge clock) #1;
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angle = '0;
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r = 120;
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x0 = 120;
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y0 = 128;
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for (int i = 0; i < 1024; i ++) begin
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@(posedge clock) #1;
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req = 1'b1;
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wait (ack);
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angle = angle + 1'b1;
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end
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req = 1'b0;
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repeat(10) @(posedge clock) #1;
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$finish;
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end
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initial begin
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$dumpfile("tb_circle.vcd");
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$dumpvars;
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end
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endmodule // tb_circle
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