38 lines
727 B
Systemverilog
38 lines
727 B
Systemverilog
`timescale 1ns/100ps
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`default_nettype none
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module lfsr #(parameter POLY = 32'hA3000000)
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(clock,
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preset,
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data_i,
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prnd_o);
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localparam WIDTH = $size(POLY);
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input wire clock;
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input wire preset;
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input wire [WIDTH-1:0] data_i;
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output wire prnd_o;
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logic [WIDTH-1:0] sreg;
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logic feedback;
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initial sreg = '1;
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assign feedback = sreg[0];
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assign prnd_o = feedback;
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integer i;
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always_ff @ (posedge clock)
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if (preset)
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sreg <= (data_i == '0) ? '1 : data_i;
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else begin
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sreg[WIDTH-1] <= feedback;
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for (i = 0; i < (WIDTH-1); i ++)
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sreg[i] <= POLY[i] ? (sreg[i+1] ^ feedback) : sreg[i+1];
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end
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endmodule // lfsr
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