32 lines
654 B
Makefile
32 lines
654 B
Makefile
VC = iverilog
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VI = vvp
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#SOURCES = ../source/lcd_320x240_spi.sv
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SOURCES = $(wildcard ../source/*.sv)
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SOURCES += ../../local/share/yosys/ice40/cells_sim.v
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VFLAGS = -g2012 -I../source
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TBS = $(wildcard tb_*.sv)
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DEFINES = -D TESTBENCH
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VCDDEPS = $(TBS:.sv=.vcd)
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BINDEPS = $(TBS:.sv=.bin)
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all: $(VCDDEPS)
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.SECONDARY:
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#.SILENT: $(VCDDEPS) $(BINDEPS) clean
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%.vcd: %.bin
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@echo "Simulate :" $(<:.bin=.sv)
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$(VI) $< #> $(<:.bin=.out)
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%.bin: %.sv $(SOURCES)
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@echo "Compile :" $(@:.bin=.sv)
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$(VC) $(VFLAGS) $(DEFINES) -D DUMPFILE=\"$(@:.bin=.vcd)\" -o $@ $< $(SOURCES)
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clean:
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@echo "Remove *.bin, *.vcd, *.out"
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rm -rf *.bin
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rm -rf *.out
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rm -rf *.vcd
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