64 lines
1.2 KiB
Systemverilog
64 lines
1.2 KiB
Systemverilog
`timescale 1ns/100ps
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module tb_lcd_spi;
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logic clock = 1'b0;
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logic reset = 1'b1;
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/* Master clock 50MHz (20ns period) */
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always #(20ns/2) clock <= ~clock;
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logic [7:0] data;
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logic push, done;
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logic sclk, sdo;
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lcd_spi #(.DATA_WIDTH(8),
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.SPI_CLK_PERIOD(16)) DUT
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(.clock, .reset,
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.data_i(data),
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.push_i(push),
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.done_o(done),
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.spi_clk_o(sclk),
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.spi_dat_o(sdo));
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int state;
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always_ff @(posedge clock)
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if (reset) begin
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push <= 1'b0;
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state <= 0;
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end
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else begin
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case (state)
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0: begin
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data <= $random;
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push <= 1'b1;
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state <= 1;
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end
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1: begin
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if (done) begin
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//data <= $random;
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push <= 1'b0;
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state <= 0;
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end
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end
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endcase
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end
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initial begin
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reset = 1'b1;
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repeat(10) @(posedge clock) #1;
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reset = 1'b0;
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repeat(1000) @(posedge clock);
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$finish;
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end
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initial begin
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$dumpfile("tb_lcd_spi.vcd");
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$dumpvars;
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end
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endmodule // tb_lcd_spi
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