95 lines
1.9 KiB
Systemverilog
95 lines
1.9 KiB
Systemverilog
`timescale 1ns/100ps
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`default_nettype none
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module ice40_spram
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(input wire clock,
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input wire [15:0] addr,
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input wire [15:0] data_i,
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output wire [15:0] data_o,
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input wire wr);
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logic [15:0] data0_o;
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logic [15:0] data1_o;
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logic [15:0] data2_o;
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logic [15:0] data3_o;
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logic w0, w1, w2, w3;
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logic [15:0] datax_o;
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assign data_o = datax_o;
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always @(*) begin
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{w0, w1, w2, w3} = '0;
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case (addr[15:14])
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2'd0: begin
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datax_o = data0_o;
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w0 = wr;
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end
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2'd1: begin
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datax_o = data1_o;
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w1 = wr;
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end
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2'd2: begin
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datax_o = data2_o;
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w2 = wr;
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end
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2'd3: begin
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datax_o = data3_o;
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w3 = wr;
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end
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endcase
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end
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SB_SPRAM256KA spram0
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(.CLOCK(clock),
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.ADDRESS(addr[13:0]),
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.DATAIN(data_i),
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.DATAOUT(data0_o),
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.WREN(w0),
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.MASKWREN({w0, w0, w0, w0}),
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.CHIPSELECT(1'b1),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b1));
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SB_SPRAM256KA spram1
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(.CLOCK(clock),
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.ADDRESS(addr[13:0]),
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.DATAIN(data_i),
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.DATAOUT(data1_o),
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.WREN(w1),
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.MASKWREN({w1, w1, w1, w1}),
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.CHIPSELECT(1'b1),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b1));
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SB_SPRAM256KA spram2
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(.CLOCK(clock),
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.ADDRESS(addr[13:0]),
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.DATAIN(data_i),
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.DATAOUT(data2_o),
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.WREN(w2),
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.MASKWREN({w2, w2, w2, w2}),
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.CHIPSELECT(1'b1),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b1));
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SB_SPRAM256KA spram3
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(.CLOCK(clock),
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.ADDRESS(addr[13:0]),
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.DATAIN(data_i),
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.DATAOUT(data3_o),
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.WREN(w3),
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.MASKWREN({w3, w3, w3, w3}),
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.CHIPSELECT(1'b1),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b1));
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endmodule // ice40_spram
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