78 lines
1.7 KiB
Systemverilog
78 lines
1.7 KiB
Systemverilog
`timescale 1ns/100ps
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/**
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* PLL configuration 12MHz->30MHz
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*
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* F_PLLOUT: 30.000 MHz (requested)
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* F_PLLOUT: 30.000 MHz (achieved)
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*
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* FEEDBACK: SIMPLE
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* F_PFD: 12.000 MHz
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* F_VCO: 960.000 MHz
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*
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* DIVR: 0 (4'b0000)
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* DIVF: 79 (7'b1001111)
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* DIVQ: 5 (3'b101)
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*
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* FILTER_RANGE: 1 (3'b001)
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*/
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`ifdef VERILATOR
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`define TESTBENCH
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`endif
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module pll
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(input clock_in,
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output clock_out,
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output locked);
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wire unused_0, unused_1;
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`ifdef TESTBENCH
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`ifdef VERILATOR
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/* In Verilator just forward clock_in to clock_out */
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assign clock_out = clock_in;
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assign locked = 1'b1;
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`else // !VERILATOR
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/* In Icarus Verilog generate new clock and 'locked' signal */
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logic clock_tb;
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logic lock_tb;
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assign clock_out = clock_tb;
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assign locked = lock_tb;
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initial begin
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clock_tb = 1'b0;
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lock_tb = 1'b0;
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repeat (100) @(posedge clock_tb);
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lock_tb = 1'b1;
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end
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always #(33ns/2) clock_tb <= ~clock_tb;
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`endif
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`else
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/* In HW use PLL primitive */
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SB_PLL40_PAD #(.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'd0),
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/* For 30 MHz: DIVF=79, DIVQ=5
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* For 50 MHz: DIVF=66, DIVQ=4 */
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.DIVF(7'd79),
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.DIVQ(3'd5),
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.FILTER_RANGE(3'd1))
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uut (.PACKAGEPIN (clock_in),
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.PLLOUTGLOBAL (clock_out),
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.EXTFEEDBACK (1'b0),
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.DYNAMICDELAY (8'b0),
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.LOCK (locked),
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.BYPASS (1'b0),
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.RESETB (1'b1),
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.LATCHINPUTVALUE(1'b0),
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.PLLOUTCORE (unused_0),
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.SDO (unused_1),
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.SDI (1'b0),
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.SCLK (1'b0));
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`endif
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endmodule
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