Add function for alignment of named port connections in module instantiations.

README.md

@@ -7,6 +7,7 @@ Align SystemVerilog ANSI-style port declarations in a contiguous block around po
 - Aligns direction, type, range, name, and trailing `//` comments.
 - Works on the contiguous block of port declarations above and below point.
 - Stops at the first non-port line (including blank lines).
+- Aligns named port connections in module instantiations via `verilog-align-ports-instantiation`.
 
 ## Installation
 
@@ -20,6 +21,11 @@ Align SystemVerilog ANSI-style port declarations in a contiguous block around po
 1. Place point on a line that declares a port (input/output/inout).
 2. Run `M-x verilog-align-ports`.
 
+For module instantiations:
+
+1. Place point on a named port connection line (e.g., `.clk_i (clk)` or `.full_o,`).
+2. Run `M-x verilog-align-ports-instantiation`.
+
 Example input:
 
 ```systemverilog