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Add function for alignment of named port connections in module instantiations.

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This commit is contained in:
Nikolay Puzanov
2026-02-08 13:39:22 +03:00
parent 6f6e4ef29b
commit 2102adc1da
3 changed files with 236 additions and 3 deletions
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74
verilog-align-ports-test.el
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@@ -66,6 +66,80 @@
(verilog-align-ports)
(should (string= (buffer-string) expected)))))
(ert-deftest verilog-align-ports-instantiation-aligns-block ()
(let* ((input (concat
(mapconcat
#'identity
'("fifo_sync #("
" .FifoWriteDepth(FifoWriteDepth),"
" .DataWidth(DataWidth),"
" .DataCountWidth(WrDataCountW),"
" .RdDataCountWidth(RdDataCountW)"
") dut ("
" .rst_i (rst), //rst"
" .clk_i (clk),"
" .wr_en_i (wr_en_i),"
" .d_i (d_i), // di"
" .full_o, // full"
" .data_count_o (wr_data_count_o),"
" .rd_en_i (rd_en_i),"
" .d_o () , // do"
" .empty_o , // empty"
" .valid_o (valid_o)"
");")
"\n")
"\n"))
(expected (concat
(mapconcat
#'identity
(list
"fifo_sync #("
" .FifoWriteDepth(FifoWriteDepth),"
" .DataWidth(DataWidth),"
" .DataCountWidth(WrDataCountW),"
" .RdDataCountWidth(RdDataCountW)"
") dut ("
(concat " .rst_i" (make-string 8 ?\s) "(rst),"
(make-string 13 ?\s) "//rst")
(concat " .clk_i" (make-string 8 ?\s) "(clk),")
(concat " .wr_en_i" (make-string 6 ?\s) "(wr_en_i),")
(concat " .d_i" (make-string 10 ?\s) "(d_i),"
(make-string 13 ?\s) "// di")
(concat " .full_o," (make-string 25 ?\s) "// full")
(concat " .data_count_o" (make-string 1 ?\s)
"(wr_data_count_o),")
(concat " .rd_en_i" (make-string 6 ?\s) "(rd_en_i),")
(concat " .d_o" (make-string 10 ?\s) "(),"
(make-string 16 ?\s) "// do")
(concat " .empty_o," (make-string 24 ?\s) "// empty")
(concat " .valid_o" (make-string 6 ?\s) "(valid_o)")
");")
"\n")
"\n")))
(with-temp-buffer
(insert input)
(goto-char (point-min))
(search-forward ".clk_i")
(beginning-of-line)
(should (verilog-align-ports-instantiation))
(should (string= (buffer-string) expected)))))
(ert-deftest verilog-align-ports-instantiation-returns-nil-outside ()
(with-temp-buffer
(insert (concat
(mapconcat
#'identity
'("fifo_sync #() dut ("
" .rst_i (rst),"
" .clk_i (clk)"
");")
"\n")
"\n"))
(goto-char (point-min))
(search-forward "dut (")
(beginning-of-line)
(should (not (verilog-align-ports-instantiation)))))
(provide 'verilog-align-ports-test)
;;; verilog-align-ports-test.el ends here