Add function for alignment of signal declarations.

README.md

@@ -8,6 +8,7 @@ Align SystemVerilog ANSI-style port declarations in a contiguous block around po
 - Works on the contiguous block of port declarations above and below point.
 - Stops at the first non-port line (including blank lines).
 - Aligns named port connections in module instantiations via `verilog-align-ports-instantiation`.
+- Aligns signal declarations via `verilog-align-ports-declarations`.
 
 ## Installation
 
@@ -26,6 +27,11 @@ For module instantiations:
 1. Place point on a named port connection line (e.g., `.clk_i (clk)` or `.full_o,`).
 2. Run `M-x verilog-align-ports-instantiation`.
 
+For signal declarations:
+
+1. Place point on a declaration line (e.g., `logic foo;` or `wire [3:0] bar;`).
+2. Run `M-x verilog-align-ports-declarations`.
+
 Example input:
 
 ```systemverilog