Add function for alignment of signal declarations.

verilog-align-ports-test.el

@@ -140,6 +140,68 @@
     (beginning-of-line)
     (should (not (verilog-align-ports-instantiation)))))
 
+(ert-deftest verilog-align-ports-declarations-aligns-block ()
+  (let* ((input (concat
+                 (mapconcat
+                  #'identity
+                  '("logic  wr_en_i;   // write enable"
+                    "logic [DataWidth-1:0]    d_i;   // data input"
+                    "logic full_o;"
+                    "logic [WrDataCountW-1:0] wr_data_count_o; // data count"
+                    "wire   rd_en_i; // read enable"
+                    "logic [DataWidth-1:0]    d_o;"
+                    "reg empty_o;// empty flag"
+                    "logic valid_o;")
+                  "\n")
+                 "\n"))
+         (expected (concat
+                    (mapconcat
+                     #'identity
+                     (list
+                      (concat "logic" (make-string 20 ?\s)
+                              "wr_en_i;" (make-string 9 ?\s)
+                              "// write enable")
+                      (concat "logic" " " "[DataWidth-1:0]" (make-string 4 ?\s)
+                              "d_i;" (make-string 13 ?\s)
+                              "// data input")
+                      (concat "logic" (make-string 20 ?\s) "full_o;")
+                      (concat "logic" " " "[WrDataCountW-1:0]" " "
+                              "wr_data_count_o;" " " "// data count")
+                      (concat "wire" (make-string 21 ?\s)
+                              "rd_en_i;" (make-string 9 ?\s)
+                              "// read enable")
+                      (concat "logic" " " "[DataWidth-1:0]" (make-string 4 ?\s)
+                              "d_o;")
+                      (concat "reg" (make-string 22 ?\s)
+                              "empty_o;" (make-string 9 ?\s)
+                              "// empty flag")
+                      (concat "logic" (make-string 20 ?\s) "valid_o;")
+                      )
+                     "\n")
+                    "\n")))
+    (with-temp-buffer
+      (insert input)
+      (goto-char (point-min))
+      (search-forward "logic full_o")
+      (beginning-of-line)
+      (should (verilog-align-ports-declarations))
+      (should (string= (buffer-string) expected)))))
+
+(ert-deftest verilog-align-ports-declarations-returns-nil-outside ()
+  (with-temp-buffer
+    (insert (concat
+             (mapconcat
+              #'identity
+              '("module foo;"
+                "logic a;"
+                "endmodule")
+              "\n")
+             "\n"))
+    (goto-char (point-min))
+    (search-forward "module foo")
+    (beginning-of-line)
+    (should (not (verilog-align-ports-declarations)))))
+
 (provide 'verilog-align-ports-test)
 
 ;;; verilog-align-ports-test.el ends here