Initial commit

README.md

@@ -0,0 +1,53 @@
+# verilog-align-ports
+
+Align SystemVerilog ANSI-style port declarations in a contiguous block around point.
+
+## Features
+
+- Aligns direction, type, range, name, and trailing `//` comments.
+- Works on the contiguous block of port declarations above and below point.
+- Stops at the first non-port line (including blank lines).
+
+## Installation
+
+```elisp
+(add-to-list 'load-path "/path/to/verilog-align-ports")
+(require 'verilog-align-ports)
+```
+
+## Usage
+
+1. Place point on a line that declares a port (input/output/inout).
+2. Run `M-x verilog-align-ports`.
+
+Example input:
+
+```systemverilog
+  input wire rst_i, // rst,
+  input wire clk_i, // wr_clk,
+  input wire [DataWidth-1:0] d_i, // din,
+  output logic full_o,  // full,
+  output [DataWidth-1:0]   d_o, // dout,
+  output empty_o,// empty,
+  output logic valid_o    // data_valid
+```
+
+Example output:
+
+```systemverilog
+  input  wire                  rst_i,   // rst,
+  input  wire                  clk_i,   // wr_clk,
+  input  wire  [DataWidth-1:0] d_i,     // din,
+  output logic                 full_o,  // full,
+  output       [DataWidth-1:0] d_o,     // dout,
+  output                       empty_o, // empty,
+  output logic                 valid_o  // data_valid
+```
+
+## Tests
+
+Run:
+
+```bash
+./run-tests.sh
+```