Initial commit

2026-02-05 14:53:00 +03:00
commit a1107b911a
4 changed files with 314 additions and 0 deletions
--- a/verilog-align-ports-test.el
+++ b/verilog-align-ports-test.el
@@ -0,0 +1,71 @@
+;;; verilog-align-ports-test.el --- Tests for verilog-align-ports -*- lexical-binding: t; -*-
+
+;;; Commentary:
+;; ERT tests for verilog-align-ports.
+
+;;; Code:
+
+(require 'ert)
+
+(defconst verilog-align-ports-test--dir
+  (file-name-directory (or load-file-name buffer-file-name)))
+
+(load-file (expand-file-name "verilog-align-ports.el"
+                             verilog-align-ports-test--dir))
+
+(ert-deftest verilog-align-ports-aligns-block ()
+  (let* ((input (concat
+                 (mapconcat
+                  #'identity
+                  '("module fifo_sync #("
+                    "  parameter integer FifoWriteDepth   = 2048,"
+                    "  parameter integer DataWidth        = 32,"
+                    "  parameter integer WrDataCountWidth = $clog2(FifoWriteDepth)+1,"
+                    "  parameter integer RdDataCountWidth = 4"
+                    ") ("
+                    "  input wire rst_i, // rst,"
+                    "  input wire clk_i, // wr_clk,"
+                    "  input wire wr_en_i, // wr_en,"
+                    "  input wire [DataWidth-1:0] d_i, // din,"
+                    "  output logic full_o,  // full,"
+                    "  output logic [WrDataCountWidth-1:0] wr_data_count_o, // wr_data_count,"
+                    "  input wire rd_en_i, // rd_en,"
+                    "  output [DataWidth-1:0]   d_o, // dout,"
+                    "  output empty_o,// empty,"
+                    "  output logic valid_o    // data_valid"
+                    ");")
+                  "\n")
+                 "\n"))
+         (expected (concat
+                    (mapconcat
+                     #'identity
+                     '("module fifo_sync #("
+                       "  parameter integer FifoWriteDepth   = 2048,"
+                       "  parameter integer DataWidth        = 32,"
+                       "  parameter integer WrDataCountWidth = $clog2(FifoWriteDepth)+1,"
+                       "  parameter integer RdDataCountWidth = 4"
+                       ") ("
+                       "  input  wire                         rst_i,           // rst,"
+                       "  input  wire                         clk_i,           // wr_clk,"
+                       "  input  wire                         wr_en_i,         // wr_en,"
+                       "  input  wire  [DataWidth-1:0]        d_i,             // din,"
+                       "  output logic                        full_o,          // full,"
+                       "  output logic [WrDataCountWidth-1:0] wr_data_count_o, // wr_data_count,"
+                       "  input  wire                         rd_en_i,         // rd_en,"
+                       "  output       [DataWidth-1:0]        d_o,             // dout,"
+                       "  output                              empty_o,         // empty,"
+                       "  output logic                        valid_o          // data_valid"
+                       ");")
+                     "\n")
+                    "\n")))
+    (with-temp-buffer
+      (insert input)
+      (goto-char (point-min))
+      (search-forward "input wire clk_i")
+      (beginning-of-line)
+      (verilog-align-ports)
+      (should (string= (buffer-string) expected)))))
+
+(provide 'verilog-align-ports-test)
+
+;;; verilog-align-ports-test.el ends here