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README.md
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README.md
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# verilog-align-ports
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Align SystemVerilog ANSI-style port declarations in a contiguous block around point.
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## Features
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- Aligns direction, type, range, name, and trailing `//` comments.
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- Works on the contiguous block of port declarations above and below point.
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- Stops at the first non-port line (including blank lines).
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## Installation
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```elisp
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(add-to-list 'load-path "/path/to/verilog-align-ports")
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(require 'verilog-align-ports)
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```
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## Usage
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1. Place point on a line that declares a port (input/output/inout).
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2. Run `M-x verilog-align-ports`.
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Example input:
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```systemverilog
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input wire rst_i, // rst,
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input wire clk_i, // wr_clk,
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input wire [DataWidth-1:0] d_i, // din,
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output logic full_o, // full,
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output [DataWidth-1:0] d_o, // dout,
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output empty_o,// empty,
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output logic valid_o // data_valid
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```
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Example output:
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```systemverilog
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input wire rst_i, // rst,
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input wire clk_i, // wr_clk,
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input wire [DataWidth-1:0] d_i, // din,
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output logic full_o, // full,
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output [DataWidth-1:0] d_o, // dout,
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output empty_o, // empty,
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output logic valid_o // data_valid
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```
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## Tests
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Run:
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```bash
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./run-tests.sh
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```
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7
run-tests.sh
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run-tests.sh
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#!/usr/bin/env bash
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set -euo pipefail
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emacs -batch \
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-l ert \
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-l verilog-align-ports-test.el \
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-f ert-run-tests-batch-and-exit
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71
verilog-align-ports-test.el
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verilog-align-ports-test.el
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;;; verilog-align-ports-test.el --- Tests for verilog-align-ports -*- lexical-binding: t; -*-
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;;; Commentary:
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;; ERT tests for verilog-align-ports.
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;;; Code:
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(require 'ert)
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(defconst verilog-align-ports-test--dir
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(file-name-directory (or load-file-name buffer-file-name)))
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(load-file (expand-file-name "verilog-align-ports.el"
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verilog-align-ports-test--dir))
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(ert-deftest verilog-align-ports-aligns-block ()
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(let* ((input (concat
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(mapconcat
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#'identity
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'("module fifo_sync #("
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" parameter integer FifoWriteDepth = 2048,"
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" parameter integer DataWidth = 32,"
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" parameter integer WrDataCountWidth = $clog2(FifoWriteDepth)+1,"
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" parameter integer RdDataCountWidth = 4"
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") ("
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" input wire rst_i, // rst,"
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" input wire clk_i, // wr_clk,"
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" input wire wr_en_i, // wr_en,"
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" input wire [DataWidth-1:0] d_i, // din,"
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" output logic full_o, // full,"
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" output logic [WrDataCountWidth-1:0] wr_data_count_o, // wr_data_count,"
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" input wire rd_en_i, // rd_en,"
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" output [DataWidth-1:0] d_o, // dout,"
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" output empty_o,// empty,"
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" output logic valid_o // data_valid"
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");")
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"\n")
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"\n"))
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(expected (concat
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(mapconcat
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#'identity
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'("module fifo_sync #("
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" parameter integer FifoWriteDepth = 2048,"
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" parameter integer DataWidth = 32,"
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" parameter integer WrDataCountWidth = $clog2(FifoWriteDepth)+1,"
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" parameter integer RdDataCountWidth = 4"
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") ("
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" input wire rst_i, // rst,"
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" input wire clk_i, // wr_clk,"
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" input wire wr_en_i, // wr_en,"
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" input wire [DataWidth-1:0] d_i, // din,"
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" output logic full_o, // full,"
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" output logic [WrDataCountWidth-1:0] wr_data_count_o, // wr_data_count,"
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" input wire rd_en_i, // rd_en,"
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" output [DataWidth-1:0] d_o, // dout,"
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" output empty_o, // empty,"
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" output logic valid_o // data_valid"
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");")
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"\n")
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"\n")))
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(with-temp-buffer
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(insert input)
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(goto-char (point-min))
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(search-forward "input wire clk_i")
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(beginning-of-line)
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(verilog-align-ports)
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(should (string= (buffer-string) expected)))))
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(provide 'verilog-align-ports-test)
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;;; verilog-align-ports-test.el ends here
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183
verilog-align-ports.el
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verilog-align-ports.el
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;;; verilog-align-ports.el --- Align SystemVerilog port declarations -*- lexical-binding: t; -*-
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;;; Commentary:
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;; Align SystemVerilog ANSI-style port declarations in a contiguous block.
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;;; Code:
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(require 'cl-lib)
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(require 'subr-x)
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(defun verilog-align-ports--line-port-p (pos)
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(save-excursion
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(goto-char pos)
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(let ((line (buffer-substring-no-properties
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(line-beginning-position)
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(line-end-position))))
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(string-match-p "^\\s-*\\(input\\|output\\|inout\\)\\b" line))))
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(defun verilog-align-ports--split-comment (line)
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(let ((pos (string-match "//" line)))
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(if pos
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(cons (substring line 0 pos) (substring line pos))
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(cons line nil))))
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(defun verilog-align-ports--parse-line (line)
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(let* ((split (verilog-align-ports--split-comment line))
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(code (string-trim-right (car split)))
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(comment (cdr split)))
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(when (string-match
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"^\\(\\s-*\\)\\(input\\|output\\|inout\\)\\b\\s-*\\(.*\\)$"
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code)
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(let* ((indent (match-string 1 code))
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(dir (match-string 2 code))
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(rest (string-trim (match-string 3 code)))
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(name nil)
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(comma nil)
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(type "")
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(range "")
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(before ""))
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(if (string-match
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"\\(\\\\[^[:space:]]+\\|[A-Za-z_][A-Za-z0-9_$]*\\)\\(\\s-*,\\)?\\s-*$"
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rest)
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(progn
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(setq name (match-string 1 rest))
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(setq comma (when (match-string 2 rest) ","))
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(setq before
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(string-trim-right (substring rest 0 (match-beginning 1)))))
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(setq name rest)
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(setq comma nil)
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(setq before ""))
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(setq before (string-trim-right before))
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(if (and (not (string-empty-p before))
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(string-match "\\(\\[[^][]+\\]\\)\\s-*$" before))
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(progn
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(setq range (match-string 1 before))
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(setq type
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(string-trim-right (substring before 0 (match-beginning 1)))))
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(setq type (string-trim before))
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(setq range ""))
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(list :indent indent
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:dir dir
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:type type
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:range range
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:name name
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:comma comma
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:comment comment)))))
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(defun verilog-align-ports--bounds ()
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(save-excursion
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(unless (verilog-align-ports--line-port-p (line-beginning-position))
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(user-error "Point is not on a port declaration line"))
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(let ((start (line-beginning-position))
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(end nil))
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(while (and (not (bobp))
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(save-excursion
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(forward-line -1)
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(verilog-align-ports--line-port-p
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(line-beginning-position))))
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(forward-line -1)
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(setq start (line-beginning-position)))
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(goto-char start)
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(while (and (not (eobp))
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(verilog-align-ports--line-port-p
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(line-beginning-position)))
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(forward-line 1))
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(setq end (line-beginning-position))
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(cons start end))))
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(defun verilog-align-ports--collect (start end)
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(let (entries)
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(save-excursion
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(goto-char start)
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(while (< (point) end)
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(let* ((line (buffer-substring-no-properties
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(line-beginning-position)
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(line-end-position)))
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(entry (verilog-align-ports--parse-line line)))
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(when entry
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(push entry entries)))
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(forward-line 1)))
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(nreverse entries)))
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(defun verilog-align-ports--max-lengths (entries)
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(let ((max-dir 0)
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(max-type 0)
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(max-range 0)
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(max-name 0)
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(has-comment nil))
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(dolist (entry entries)
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(setq max-dir (max max-dir (length (plist-get entry :dir))))
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(setq max-type (max max-type (length (plist-get entry :type))))
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(setq max-range (max max-range (length (plist-get entry :range))))
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(let ((name (concat (plist-get entry :name)
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(or (plist-get entry :comma) ""))))
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(setq max-name (max max-name (length name))))
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(when (plist-get entry :comment)
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(setq has-comment t)))
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(list max-dir max-type max-range max-name has-comment)))
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(defun verilog-align-ports--pad (max-len len)
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(make-string (+ 1 (- max-len len)) ?\s))
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(defun verilog-align-ports--format-lines (entries)
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(let* ((base-indent (plist-get (car entries) :indent))
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(maxes (verilog-align-ports--max-lengths entries))
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(max-dir (nth 0 maxes))
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(max-type (nth 1 maxes))
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(max-range (nth 2 maxes))
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(max-name (nth 3 maxes))
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(has-comment (nth 4 maxes))
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(has-type (> max-type 0))
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(has-range (> max-range 0)))
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(mapcar
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(lambda (entry)
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(let* ((dir (plist-get entry :dir))
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(type (plist-get entry :type))
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(range (plist-get entry :range))
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(name (concat (plist-get entry :name)
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(or (plist-get entry :comma) "")))
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(comment (plist-get entry :comment))
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(dir-pad (verilog-align-ports--pad max-dir (length dir)))
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(type-pad (when has-type
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(verilog-align-ports--pad max-type (length type))))
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(range-pad (when has-range
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(verilog-align-ports--pad max-range (length range))))
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(name-pad (when (and has-comment comment)
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(verilog-align-ports--pad max-name (length name)))))
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(concat base-indent
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dir
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dir-pad
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(when has-type type)
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(when has-type type-pad)
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(when has-range range)
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(when has-range range-pad)
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name
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(when (and has-comment comment) name-pad)
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(or comment ""))))
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entries)))
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(defun verilog-align-ports--apply (start lines)
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(save-excursion
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(goto-char start)
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(dolist (line lines)
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(delete-region (line-beginning-position) (line-end-position))
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(insert line)
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(forward-line 1))))
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;;;###autoload
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(defun verilog-align-ports ()
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"Align SystemVerilog port declarations around point."
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(interactive)
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(let* ((bounds (verilog-align-ports--bounds))
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(start (car bounds))
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(end (cdr bounds))
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(entries (verilog-align-ports--collect start end)))
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(when (null entries)
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(user-error "No port declarations found"))
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(let ((lines (verilog-align-ports--format-lines entries)))
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(verilog-align-ports--apply start lines))))
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(provide 'verilog-align-ports)
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;;; verilog-align-ports.el ends here
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