np/verilog-playground
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Fix signals sorting (put clock on the top)

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This commit is contained in:
Nikolay Puzanov 2022-12-07 17:53:50 +03:00
parent 90905544d4
commit 931f4d8aa4
1 changed files with 9 additions and 10 deletions
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7
_web_server/server/playground-server.scm
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@ -343,10 +343,9 @@
(let ((tstart (apply min (vcd-timestamps vcd))) (let ((tstart (apply min (vcd-timestamps vcd)))
(tend (apply max (vcd-timestamps vcd))) (tend (apply max (vcd-timestamps vcd)))
(signals (sort (signals (sort
(remove (vcd-signals vcd)
(lambda (sig) (< (length (vcd-signal-scope sig)) 2))
(vcd-signals vcd))
(lambda (a b) (lambda (a b)
(and (not (equal? (vcd-signal-name b) "clock"))
(or (or
(and (equal? (vcd-signal-name a) "clock") (and (equal? (vcd-signal-name a) "clock")
(not (equal? (vcd-signal-name b) "clock"))) (not (equal? (vcd-signal-name b) "clock")))
@ -355,7 +354,7 @@
(length (vcd-signal-scope b))) (length (vcd-signal-scope b)))
(string-ci<? (vcd-signal-name a) (string-ci<? (vcd-signal-name a)
(vcd-signal-name b))))))) (vcd-signal-name b))))))))
(if (<= tend tstart) (if (<= tend tstart)
'() '()