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Remove clock from testbench input

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This commit is contained in:
Nikolay Puzanov 2024-04-14 16:08:20 +03:00
parent 1e0bfb58cf
commit b84ec9a1c5
3 changed files with 41 additions and 53 deletions
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18
_web_server/server/playground-server.scm
View File

@ -33,7 +33,7 @@
(define IVERILOG-EXE "iverilog") (define IVERILOG-EXE "iverilog")
(define VVP-EXE "vvp") (define VVP-EXE "vvp")
(define VERILATR-EXE "verilator") (define VERILATOR-EXE "verilator")
(define URI-IVERILOG "iverilog") (define URI-IVERILOG "iverilog")
(define URI-VERILATOR "verilator") (define URI-VERILATOR "verilator")
@ -49,9 +49,14 @@
(define DEFAULT-CODE (define DEFAULT-CODE
(string-append (string-append
"`timescale 1ps/1ps\n\n" "`timescale 1ps/1ps\n\n"
(format "module ~a (input clock);\n" TOP-MODULE) ;; (format "module ~a (input clock);\n" TOP-MODULE)
(format "module ~a;\n" TOP-MODULE)
" logic clock = 1'b0;\n"
" initial forever #(5ns) clock = ~clock;\n"
"\n"
" initial begin\n" " initial begin\n"
" $display(\"Hello world!\");\n" " $display(\"Hello world!\");\n"
" repeat(10) @(posedge clock);\n"
" $finish();\n" " $finish();\n"
" end\n" " end\n"
"endmodule\n")) "endmodule\n"))
@ -566,8 +571,7 @@
(with-output-to-file command-file (with-output-to-file command-file
(lambda () (lambda ()
(println "+define+TESTBENCH") (println "-DTESTBENCH")
(println "-CFLAGS -fcoroutines")
(println "--timescale 1ps/1ps") (println "--timescale 1ps/1ps")
(println "--top-module ~a" top) (println "--top-module ~a" top)
(println "--Mdir ~a" (path+ work-dir top)) (println "--Mdir ~a" (path+ work-dir top))
@ -580,7 +584,7 @@
(println "--build") (println "--build")
(println "-sv") (println "-sv")
(println "-Wno-WIDTH") (println "-Wno-WIDTH")
(println "+1800-2017ext+sv") (println "+1800-2023ext+sv")
(println "--timing") (println "--timing")
(println "--trace") (println "--trace")
(println "--trace-structs") (println "--trace-structs")
@ -650,7 +654,7 @@
(let* ((command-file (path+ work-dir (format "~a.vc" top))) (let* ((command-file (path+ work-dir (format "~a.vc" top)))
(vcd-file (path+ work-dir (format "~a.vcd" top))) (vcd-file (path+ work-dir (format "~a.vcd" top)))
(cmds `(,(format "~a -f ~a" (cmds `(,(format "~a -f ~a"
(wrap-exe VERILATR-EXE verilator-wrap) (wrap-exe VERILATOR-EXE verilator-wrap)
command-file) command-file)
,(wrap-exe (path+ work-dir (format "~a/~a" top top)) ,(wrap-exe (path+ work-dir (format "~a/~a" top top))
verilator-sim-wrap)))) verilator-sim-wrap))))
@ -818,7 +822,7 @@
,(format "Icarus: ~a" ,(format "Icarus: ~a"
(app-version (wrap-exe IVERILOG-EXE iverilog-wrap) "-V")) (app-version (wrap-exe IVERILOG-EXE iverilog-wrap) "-V"))
,(format "Verilator: ~a" ,(format "Verilator: ~a"
(app-version (wrap-exe VERILATR-EXE verilator-wrap))) (app-version (wrap-exe VERILATOR-EXE verilator-wrap)))
"" ""
"Rules:" "Rules:"
"0. Don't fool around ;)" "0. Don't fool around ;)"

5
_web_server/server/top_iverilog.sv
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@ -1,9 +1,8 @@
`timescale 1ps/1ps `timescale 1ps/1ps
module __@TOPMODULE@__; module __@TOPMODULE@__;
logic clock = 1'b0; @TOPMODULE@ @TOPMODULE@ ();
initial forever #(5ns) clock = ~clock;
@TOPMODULE@ @TOPMODULE@ (clock);
initial begin initial begin
$dumpfile("@WORKDIR@/@TOPMODULE@.vcd"); $dumpfile("@WORKDIR@/@TOPMODULE@.vcd");
$dumpvars(1, @TOPMODULE@); $dumpvars(1, @TOPMODULE@);

69
_web_server/server/top_verilator.cpp
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@ -1,58 +1,43 @@
#include "verilated.h"
#include "verilated_vcd_c.h"
#include "V@TOPMODULE@.h" #include "V@TOPMODULE@.h"
#include <cstdint>
#include <verilated.h>
#include <verilated_vcd_c.h>
#define DUMPFILE "@WORKDIR@/@TOPMODULE@.vcd" #define DUMPFILE "@WORKDIR@/@TOPMODULE@.vcd"
#define CLOCK_HALF_PERIOD 5000
int main(int argc, char **argv) int main(int argc, char** argv, char**) {
{ // Setup context, defaults, and parse command line
VerilatedContext *ctx = new VerilatedContext; Verilated::debug(0);
ctx->commandArgs(argc, argv); const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
contextp->traceEverOn(true);
contextp->commandArgs(argc, argv);
/* Create model instance */ // Construct the Verilated model, from Vtop.h generated from Verilating
V@TOPMODULE@ *top = new V@TOPMODULE@(ctx); const std::unique_ptr<V@TOPMODULE@> topp{new V@TOPMODULE@{contextp.get()}};
#if (VM_TRACE == 1)
VerilatedVcdC *vcd = new VerilatedVcdC; VerilatedVcdC *vcd = new VerilatedVcdC;
ctx->traceEverOn(true); topp->trace(vcd, 99);
top->trace(vcd, 99);
vcd->open(DUMPFILE); vcd->open(DUMPFILE);
#endif
top->clock = 0; // Simulate until $finish
while (!contextp->gotFinish()) {
/* ---- Evaluation loop ---- */ // Evaluate model
for (;;) { topp->eval();
/* Eval */ vcd->dump(contextp->time());
top->eval(); // Advance time
if (!topp->eventsPending()) break;
/* Trace steady-state values */ contextp->time(topp->nextTimeSlot());
#if (VM_TRACE == 1)
if (vcd) vcd->dump(ctx->time());
#endif
/* Break exactly after calling $finish */
if (ctx->gotFinish()) break;
/* Clock event */
ctx->timeInc(CLOCK_HALF_PERIOD);
top->clock = top->clock ? 0 : 1;
} }
top->final(); if (!contextp->gotFinish()) {
printf("[%lu] Stop simulation\n", ctx->time()); VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n"););
}
#if (VM_TRACE == 1) // Execute 'final' processes
if (vcd) { topp->final();
// Print statistical summary report
contextp->statsPrintSummary();
vcd->close(); vcd->close();
delete vcd;
}
#endif
delete top;
delete ctx;
return 0; return 0;
} }