24 lines
550 B
Makefile
24 lines
550 B
Makefile
TOP_MODULE = top
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SOURCES = top.sv top.cpp clock_generator.cpp
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INCLUDES =
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## Parameters example:
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# PARAM_INPUT_WIDTH ?= 15
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# PARAM_FFT_LENGTH ?= 256
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# PARAM_REJECTOR_K_WIDTH ?= 8
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FLAGS = -Wno-WIDTH -cc --top-module $(TOP_MODULE) +1800-2017ext+sv --timing --trace --Mdir $(TOP_MODULE)
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FLAGS += $(foreach V,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(V))=$($(V)))
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all: $(SOURCES)
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verilator $(FLAGS) --exe --build $(INCLUDES) $(SOURCES)
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pre:
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verilator $(FLAGS) $(INCLUDES) $(SOURCES)
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clean:
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rm -rf obj_dir
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rm -rf datapath
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rm -rf *.vcd
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